12 CPU circuit pack
Table 2–1
ECAC alarm reporting priority sequence – LED display codes
LED
Level
E.
d.
3
C.
2
b.
1
A.
0
9.
3
8.
2
7.
1
6.
0
5.
3
4.
2
3.
1
2.
0
1.
=.
297-1001-536 Standard 01.03 August 1996
Category
Response
Major
Invalid CPU
Response
Critical
Critical
Level 3
Critical
Critical
Level 2
Critical
Critical
Level 1
Critical
Critical
Level 0
Major
Major
Level 3
Major
Major
Level 2
Major
Major
Level 1
Major
Major
Level 0
Minor
Minor
Level 3
Minor
Minor
Level 2
Minor
Minor
Level 1
Minor
Minor
Level 0
None
None
End
Notes
Processor switch occurs.
Processor switch occurs.
Processor switch occurs.
Level 0 alarms are alarms only,
with no accompanying
processor switch.
Processor switch occurs.
Processor switch occurs.
Processor switch occurs.
Level 0 alarms are alarms only,
with no accompanying
processor switch.
Processor switch occurs.
Processor switch occurs.
Processor switch occurs.
Level 0 alarms are alarms only,
with no accompanying
processor switch.
Planned processor switch.
All systems operational.
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