SOLTEK SL-65MIE User Manual page 62

65MIE
SDRAM CAS Latency When synchronous DRAM is installed, the number of
Time clock cycles of CAS latency depends on the DRAM
timing. Do not reset this field from the default value
specified by the system designer.
SDRAM Cycle Time Select the number of SCLKs for an access cycle.
Tras/Trc The choice: 5/7; 7/9.
SDRAM RAS-To-CAS This field lets you insert a timing delay between the
Delay CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed. Fast gives faster
p e r f o r m a n c e a n d S l o w g i v e s m o r e s t a b l e
performance. This field applies only when synchro-
nous DRAM is installed in the system.
The Choice: 2; 3.
SDRAM RAS If an insufficient number of cycles is allowed for the
Precharge Time RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may
fail to retain data. Fast gives faster performance; and
Slow gives more stable performance. This field ap-
plies only when synchronous DRAM is installed in
the system.
The Choice: 2; 3.
System BIOS Selecting Enabled allows caching of the system BIOS
Cacheable ROM at F0000h-FFFFFh, resulting in better system
performance.
Video BIOS Cacheable Selecting Enabled allows caching of the system BIOS
ROM at C0000h to C7FFFh, resulting in video
performance. However, if any program writes to this
memory area, a system error may result.
Memory Hole At 15M- You can reserve this area of system memory for ISA
16M adapter ROM. When this area is reserved, it cannot
be cached. The user information of peripherals that
need to use this area of system memory usually dis-
cusses their memory requirements.
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