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NXP Semiconductors MKE1xF512VLL16 Reference Manual (1483 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 12 MB

Table of Contents
3
About this Manual
47
Audience
47
Organization
47
Module Descriptions
47
Example: Chip-Specific Information that Supersedes Content in the same Chapter
48
Example: Chip-Specific Information that Refers to a Different Chapter
49
Register Descriptions
50
Conventions
51
Numbering Systems
51
Typographic Notation
51
Special Terms
52
Introduction
53
Overview
53
Block Diagram
53
Module Functional Categories
54
Core Overview
57
ARM Cortex-M4
57
Core Buses and Interfaces
58
Core Component Configuration
59
Systick Clock Configuration
59
Interrupts
61
Introduction
61
NVIC Configuration
61
Interrupt Priority Levels
61
Non-Maskable Interrupt
62
Interrupt Channel Assignments
62
Determining the Bitfield and Register Location for Configuring a Particular Interrupt
66
System Integration Module (SIM)
67
Introduction
67
Features
67
Memory Map and Register Definition
67
Chip Control Register (SIM_CHIPCTL)
68
FTM Option Register 0 (SIM_FTMOPT0)
70
ADC Options Register (SIM_ADCOPT)
72
FTM Option Register 1 (SIM_FTMOPT1)
74
System Device Identification Register (SIM_SDID)
76
Platform Clock Gating Control Register (SIM_PLATCGC)
77
Flash Configuration Register 1 (SIM_FCFG1)
78
Flash Configuration Register 2 (SIM_FCFG2)
81
Unique Identification Register High (SIM_UIDH)
82
Unique Identification Register MID-High (SIM_UIDMH)
82
Unique Identification Register MID Low (SIM_UIDML)
83
Unique Identification Register Low (SIM_UIDL)
83
System Clock Divider Register 4 (SIM_CLKDIV4)
84
Miscellaneous Control Register (SIM_MISCTRL)
85
Miscellaneous Control Module (MCM)
87
Introduction
87
Features
87
Memory Map/Register Descriptions
87
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
88
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
89
Core Platform Control Register (MCM_CPCR)
89
Interrupt Status and Control Register (MCM_ISCR)
91
Store Buffer Fault Address Register (MCM_FADR)
94
Store Buffer Fault Attributes Register (MCM_FATR)
94
Store Buffer Fault Data Register (MCM_FDR)
96
Process ID Register (MCM_PID)
97
Compute Operation Control Register (MCM_CPO)
98
Local Memory Descriptor Register (Mcm_Lmdrn)
99
LMEM Parity & ECC Control Register (MCM_LMPECR)
103
LMEM Parity & ECC Interrupt Register (MCM_LMPEIR)
104
LMEM Fault Address Register (MCM_LMFAR)
105
LMEM Fault Attribute Register (MCM_LMFATR)
106
LMEM Fault Data High Register (MCM_LMFDHR)
107
LMEM Fault Data Low Register (MCM_LMFDLR)
107
Functional Description
108
Interrupts
108
Crossbar Switch Lite (AXBS-Lite)
109
Chip-Specific Information for this Module
109
Instantiation Information
109
Introduction
110
Features
110
Memory Map / Register Definition
110
Functional Description
110
General Operation
111
Arbitration
111
Initialization/Application Information
113
Memory Protection Unit (MPU)
115
Chip-Specific Information for this Module
115
Instantiation Information
115
Introduction
116
Overview
116
Block Diagram
116
Features
117
Memory Map/Register Definition
118
Control/Error Status Register (MPU_CESR)
120
Error Address Register, Slave Port N (Mpu_Earn)
121
Error Detail Register, Slave Port N (Mpu_Edrn)
122
Region Descriptor N, Word 0 (Mpu_Rgdn_Word0)
123
Region Descriptor N, Word 1 (Mpu_Rgdn_Word1)
124
Region Descriptor N, Word 2 (Mpu_Rgdn_Word2)
124
Region Descriptor N, Word 3 (Mpu_Rgdn_Word3)
127
Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
128
Functional Description
130
Access Evaluation Macro
130
Putting It All Together and Error Terminations
132
Power Management
133
Initialization Information
133
Application Information
133
Usage Guide
135
MPU Access Violation Indications
135
Reset Values for RGD0 Registers
136
Write Access Restrictions for RGD0 Registers
136
Peripheral Bridge (AIPS-Lite)
139
Chip-Specific Information for this Module
139
Peripheral Slot Assignment
139
Introduction
139
Features
140
General Operation
140
Memory Map/Register Definition
140
Master Privilege Register a (AIPS_MPRA)
141
Peripheral Access Control Register (Aips_Pacrn)
144
Off-Platform Peripheral Access Control Register (Aips_Opacrn)
149
Peripheral Access Control Register (AIPS_PACRU)
154
Functional Description
155
Access Support
155
Trigger MUX Control (TRGMUX)
157
Chip-Specific Information for this Module
157
Module Interconnectivity
157
Introduction
162
Features
162
Functional Description
162
Memory Map and Register Definition
162
TRGMUX0 Register Descriptions
162
TRGMUX1 Register Descriptions
201
Usage Guide
207
ADC Trigger Source
207
CMP Window/Sample Input
208
FTM Fault Detection Input / Hardware Triggers and Synchronization
208
Direct Memory Access Multiplexer (DMAMUX)
209
Chip-Specific Information for this Module
209
Instantiation Information
209
Introduction
212

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NXP Semiconductors MKE1xF512VLL16 Reference Manual (1483 pages)

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