GE MAC 5500 Service Manual page 38

Equipment Overview: Theory of Operation
unsynchronized, they would often cross two successive display frames and result in
visible tearing or flicker. As a result of this frame synchronous operation, fills
always take one frame time, regardless of their size, and complete coincident with
the end of the frame.
Main State Machine – The SDRAM frame buffer is constantly in demand by the
CPU, the video timing controller and the fill engine. The CPU manipulates pixels in
the frame buffer in real time to construct the visible display while the video timing
controller manages the constant stream of pixels from the frame buffer into the line
buffer, and on to the scroller/CLUT. At the same time, any requested fills must
access the frame buffer to write the requested fill region. When all three contend for
access to the frame buffer simultaneously, memory bandwidth can exceed
100Mbytes/sec.
The Main State Machine manages all these competing requests on a priority basis,
with display refresh taking top priority, followed by fills and finally CPU accesses.
The state machine runs at 60Mhz, processing line buffer fill requests from the video
timing generator, fill requests from the fill engine and read/write requests from the
CPU. The 5.3 pack/unpack logic and fill engine logic are actually various states of
the Main State Machine.
Interrupt Management – The LCD controller produces two interrupts to notify the
CPU of the completion of important tasks. At the end of the active region of each
display frame, the controller can generate an interrupt to tell the CPU it has
uncontested access to the frame buffer for a short period, and to synchronize display
related processes in the CPU (such as waveform drawing and scrolling control). A
similar interrupt is provided to signal the completion of fills. Both interrupts may be
disabled and/or acknowledged in the system control registers.
Video Waveform Scroller
There are numerous ways of achieving a scrolling waveform, none of which is
supported by standard LCD controllers. The MAC 5500 provides scrolling through
FPGA hardware placed between the LCD controller output and the LCD panel
input.
To produce the scrolling effect it is necessary to maintain two virtual image planes,
one atop the other. Static (stationary) objects are drawn in the static plane, which
appears nearest the viewer and may be either opaque or transparent. Dynamic
(scrolling) objects are drawn in the dynamic plane, which appears behind the static
plane and is always opaque, though not necessarily visible. The appearance of
motion is achieved by continuously changing the start point for display of the
dynamic plane from one video frame to the next.
Since the LCD controller does not support multiple image planes, it is necessary to
pack two planes of image data into a single frame buffer. On the software side
(during drawing) this is done by bit masking operations that allow separate
manipulation of two virtual pixels in each byte of frame buffer memory. Each 8-bit
byte holds a pair of pixels, one from the static plane and one from the dynamic
plane.
On the hardware side, part of each frame buffer byte (the static plane) is played
directly into the LCD after suitable color mapping. The remainder of the byte (the
dynamic plane) is stored in a 1 line temporal buffer before being displayed. The
amount of delay applied to the line buffer before merging it with the static image
data determines its placement on the screen. By gradually changing the delay, the
dynamic image can be made to scroll.
2-20 MAC 5500 resting ECG analysis system Revision E
2020299-020