GE MAC 5500 Service Manual page 37

Revision E
Equipment Overview: Theory of Operation
maintain that speed for more than one SDRAM page (256 pixels). At page
boundaries, the SDRAM must initiate a new page access, and potentially satisfy
refresh requirements. Since video lines are longer (640 pixels) than SDRAM pages,
some mechanism is required to smooth the flow of pixels from the frame buffer to
the LCD.
This smoothing is provided by a 1024 byte dual port line buffer, implemented in a
pair of FPGA block RAMs. At the end of each active LCD line, the video timing
generator requests a new line of pixels from the frame buffer. The memory arbiter
services the request by bursting 640 pixels from the frame buffer to the line buffer,
using the video address supplied by the timing controller. The entire line of 640
pixels is moved at maximum memory speed, taking a little over 11µs to complete at
60Mhz. The pixels are then clocked out of the line buffer and presented to the
scroller/CLUT at a constant 24Mhz, taking about 30µs per line. Double buffering is
not required, as the burst fill rate far exceeds the 24Mhz drain rate, and the fill
begins during the generation of horizontal sync, giving the controller plenty of head
start on filling the line buffer before the timing generator begins draining them out.
To keep the control logic simple, and minimize SDRAM access overhead, each 640
pixel line is transferred from SDRAM in one transaction. This does hold off the
ARM CPU for up to 11µs at a time, but as the ARM CPU does not access the frame
buffer often, this is not thought to be an issue.
Fill Engine – The 5500 routinely draws rectangular regions on screen for use in
dialog boxes and buttons. When drawn by the CPU, frame buffer bandwidth
becomes an issue, as random accesses to the SDRAM buffer are inefficient, and
many of them are required to fill large regions of the display. To reduce both CPU
and frame buffer loading, the LCD controller provides a simple fill engine which
automates the filling of rectangular regions of the frame buffer, and takes advantage
of the burst capabilities of the SDRAM.
The fill engine interface is simple, consisting of four boundary registers to define the
fill region, and one register to record the fill value, and planes to be filled. The fill
engine can fill any value into any rectangular region of the display in either or both
planes simultaneously. The bounding values (top, bottom, left, right) define the
rectangle to be filled in screen coordinates, with 0,0 at the upper left, and 639,479 at
the bottom right. The fill value contains both the dynamic (5) and static (3) pixel bits
as well as two plane enable bits.
After loading the boundary control registers, the CPU initiates the fill by writing the
requested fill value and plane enable bits to the fill value register. The fill is then
queued for the next video frame and the fill engine becomes "busy".
Fills are implemented synchronous with frame refresh. At the completion of each
line buffer fill request from the video timing generator the fill engine checks to see if
a fill is underway. If so, the current video line position (from the timing generator) is
compared to the top and bottom boundary registers. If the current line is between the
top and bottom, the fill engine adds the left boundary value to the current line
memory address (as provided by the timing generator) and proceeds to write the fill
value into memory until the address matches the right boundary. Depending on the
width of the filled rectangle, fill bursts can take anywhere from 100ns to 11µs.
In this way, the fill engine follows the video timing generator down the screen,
replacing pixels in the frame buffer immediately after they are sent to the LCD. This
synchronous operation makes efficient use of the existing address generation
hardware and provides "flicker-free" fills, regardless of region size. If fills were
MAC 5500 resting ECG analysis system
2020299-020
2-19