Transceiver Dpd Overview - Analog Devices ADRV9029 User Manual

Preliminary Technical
Data

TRANSCEIVER DPD OVERVIEW

The DPD feature on this transceiver enables users to offload power amplifier linearization tasks from the baseband processor to
the transceiver. With DPD implemented on the transceiver, the user does not need to allocate JESD serializer/de-serializer
resources for observing power amplifier feedback data through the ORx channels, resulting in significant system power savings.
Interpolators leading to the DPD actuator allow the baseband processor to transmit data at a lower rate on the JESD204B/C link
than is needed for the full DPD correction bandwidth. The lower data rate at JESD translates directly into power savings and less
number of lanes. Integration of the DPD into the transceiver chip results in significant system level cost, space, and power savings
when compared to conventional FPGA/ASIC based implementations.
A simplified block diagram of the transceiver DPD system is shown in Figure 4. A brief description of the individual blocks is
provided below.
Transmit Datapath – The digital baseband signal from the JESD de-framer output goes through an optional Crest Factor
Reduction (CFR) block for reduction of the overall peak to average power ratio(PAPR) of the signal followed by a digital
•
interpolation filter which interpolates the baseband signal by a factor of 1x, 2x or 4x for analyzing the baseband signal over
the DPD analysis bandwidth. The inverse PA model is applied by the DPD engine, followed by the rest of the transmit signal
chain including digital to analog conversion, up conversion by a mixer before the signal is fed into the actual amplifier.
Observation Datapath – The DPD algorithm relies on observing the non-linearities via a feedback path. The feedback path
is realized using an integrated observation receiver (ORx). The PA output data is sampled through the observation receiver,
•
down converted and digitized for further analysis by the firmware.
DPD Processing - The DPD engine is based on an abbreviated implementation of generalized memory polynomial (GMP)
that is a generalized subset of the well-known Volterra series. The simplified polynomial models a large number of PA
•
characteristics such as weak nonlinearities, temperature variation, and memory effects. The inverse PA model is applied on
the interpolated digital baseband samples through DPD actuator hardware. A dedicated embedded ARM processor (ARM-D)
is used for computation of the GMP coefficients.
ADRV9029 DPD
HB
Data From
1,2
CFR
HW ACCEL
The DPD actuator implements a programmable GMP calculator captured in the equation below.
DPD Actuator Overview
To compensate for memory effects in a large bandwidth signal, a higher order polynomial is required. The DPD actuator can be
programmed to support up to 190 coefficients for wide bandwidth signals. The structure of the DPD actuator is shown in Figure
5. For every pre-distorted output, the GMP model calculates the Sum of Product expression. The product terms consists of a
modeling coefficient c magnitude power term |x(n-i)|
terms can utilize up to 31 look-up-tables (LUT) on one specified bank. The LUTs are 1k samples deep and organized in four banks
i,j,k,
of 8-bit tables (256 entries). Please refer to the GMP Model and Transceiver Look Up Table section for more information on the
mapping GMP terms to LUTs.
DPD Actuator
HB
-1
PA
1,2
Model
Firmware
ARM-C, ARM-D
Figure 4. Simplified Block Diagram of Transceiver DPD
, and cross memory term x(n-j). Each DPD model consisting of GMP
k
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Tx PA
ORx
FILTER/DUPLEXER