Tews Technologies TPCE636 Manuals

Manuals and User Guides for Tews Technologies TPCE636. We have 1 Tews Technologies TPCE636 manual available for free PDF download: User Manual

Tews Technologies TPCE636 User Manual (104 pages)

Reconfigurable FPGA with 16x 16bit Analog Input and 16x 16bit Analog Output

Brand: Tews Technologies | Category: I/O Systems | Size: 1 MB

Table of Contents
4
Product Description
9
Figure 1-1 : Block Diagram
9
Technical Specification
10
Table 2-1 : Technical Specification
11
Handling and Operation Instruction
12
ESD Protection
12
Thermal Considerations
12
Pci Device Topology
13
Figure 4-1 : Pcie/Pci Device Topology
13
Table 4-1 : On-Board Pcie / Pci Devices
13
User FPGA (Kintex-7)
14
BCC (Board Configuration Controller) FPGA
14
PCI Configuration Registers (PCR)
14
PCI BAR Overview
14
Table 4-2 : Pci Configuration Registers
14
Table 4-3 : Pci Bar Overview
14
Local Configuration Register Space
15
In-System Programming Data Space
16
Table 4-4 : Local Configuration Register Space
16
Table 4-5 : Register Bit Access Types
16
Register Description
17
User FPGA (Kintex-7)
17
BCC (Board Configuration Controller) FPGA
18
DAC Control / Status Register - 0X00
18
Table 5-1 : Dac Control and Status Register
18
DAC Output Voltage Range Register - 0X04
19
Table 5-2 : Dac Output Voltage Range Register
19
Reference DAC Voltage Control Register - 0X10 to 0X4C
20
Figure 5-1 : Dac and Ref. Dac Schemata
20
Figure 5-2 : Dac Output Channel
20
Table 5-3 : Reference Dac Voltage Control Register
20
Table 5-4 : Voltage Coding for the Reference Dac
21
User FPGA JTAG Control and Status Register - 0X80
22
Table 5-5 : User Fpga Jtag Control and Status Register
22
User FPGA JTAG Signal Line Register - 0X84
23
User FPGA JTAG TMS Data Register - 0X88
24
User FPGA JTAG TDI Data Register - 0X8C
24
Table 5-6 : User Fpga Jtag Signal Line Register
24
Table 5-7 : User Fpga Jtag Tms Data Register
24
Table 5-8 : User Fpga Jtag Tdi Data Register
24
User FPGA JTAG TDO Data Register - 0X90
25
I2C Bridge Register - 0Xa0
25
Interrupt Enable Register - 0Xc0
25
Table 5-9 : User Fpga Jtag Tdo Data Register
25
Table 5-10 : I2C Bridge Register
25
Table 5-11 : Interrupt Enable Register
25
Interrupt Status Register - 0Xc4
26
User FPGA Configuration Control/Status Register - 0Xd0
26
Table 5-12 : Interrupt Status Register
26
Table 5-13 : User Fpga Configuration Control/Status Register
26
User FPGA Configuration Data Register - 0Xd4
27
ISP Control Register - 0Xe0
27
Table 5-14 : User Fpga Configuration Data Register
27
Table 5-15 : Isp Control Register
27
ISP Configuration Register - 0Xe4
28
ISP Command Register - 0Xe8
28
Table 5-16 : Isp Configuration Register
28
Table 5-17 : Isp Command Register
28
ISP Status Register - 0Xec
29
Table 5-18 : Isp Status Register
29
TPCE636 Temperature Sensor Register - 0Xf4
30
TPCE636 Serial Number - 0Xf8
30
Table 5-19 : Tpce636 Temperature Sensor Register
30
Table 5-20 : Tpce636 Serial Number
30
BCC - FPGA Code Version - 0Xfc
31
Table 5-21: Bcc - Fpga Code Version
31
Interrupts
32
Interrupt Sources
32
User FPGA (Kintex-7)
32
BCC (Board Configuration Controller) FPGA
32
Interrupt Handling
32
Functional Description
33
User FPGA Block Diagram
33
Figure 7-1 : Fpga Block Diagram
33
User FPGA Highlights
34
Table 7-1 : Tpce636 Fpga Feature Overview
34
Table 7-2 : Fpga Bank Usage
34
User FPGA Gigabit Transceiver (MGT)
35
Figure 7-2 : Mgt Block Diagram
35
Table 7-3 : Mgt Connections
35
Table 7-4 : Multi Gigabit Transceiver Reference Clocks
36
User FPGA Configuration
37
Master Serial SPI Flash Configuration
37
Manually User FPGA SPI Flash Reconfiguration
38
Slave Select Map Configuration
39
Configuration Via JTAG
41
User JTAG Chain
41
TEWS Factory JTAG Chain
41
Figure 7-3 : User Jtag-Chain
41
Figure 7-4 : Tews Factory Jtag-Chain
41
Programming User FPGA SPI Configuration Flash
42
Erasing User FPGA SPI Configuration Flash
43
Sector Erasing User FPGA SPI Configuration Flash
44
Reading User FPGA SPI Configuration Flash
45
BCC (Board Configuration Controller) FPGA
46
I2C Interface to BCC Register
46
Table 7-5: User Fpga I2C Interface to Bcc
46
Clocking
47
FPGA Clock Sources
47
Figure 7-5 : Fpga Clock Sources
47
Table 7-6 : Available Fpga Clocks
48
Si514 Free Programming Clock Source
49
Table 7-7 : Fpga I2C Si514 Connections
49
Back I/O Interface
50
Table 7-8 : Digital Back I/O Interface
51
Memory
52
Ddr3 Sdram
52
Table 7-9 : Ddr3 Sdram Interface
53
SPI-Flash
55
I2C - Eeprom
55
Table 7-10 : Fpga Spi-Flash Connections
55
Table 7-11: Fpga I2C Eeprom Connections
55
I2C Calibration Data
56
ADC and DAC Calibration Data Values
56
Table 7-12: Adc Calibration Data Values
56
DAC Calibration Data Values
57
Table 7-13: Dac Calibration Data Values
57
ADC Data Correction Formula
58
DAC Data Correction Formula
58
Serial ADC Interface
59
Overview
59
Figure 7-6 : Analog Input Section
59
Figure 7-7 : Analog Input Block Diagram
59
ADC Digital Output Coding
60
Table 7-14: Adc Data Coding Example
60
Table 7-15: Adc Data Coding
60
User FPGA Pinning
61
Table 7-16: Adc Interface Connections
63
Programming Hints LTC2323-16
64
Figure 7-8 : Digital Adc to Fpga Interface
64
Figure 7-9 : Timing Diagram Ltc2323-16
64
Parallel DAC Interface
65
Overview
65
Figure 7-10 : Analog Output Section
65
Figure 7-11 : Analog Output Section
65
User FPGA Pinning
66
Table 7-17: Tpce636 Parallel Dac Interface
67
Programming Hints for AD5547
68
Output Voltage Range
69
Digital Interface to Firefly Connector
70
Table 7-18 : Firefly Back I/O Interface
70
JTAG Controller to K7 JTAG Interface
71
Bit-IO
71
Vector-IO
71
I2C Bridge
72
Figure 7-12 : User Fpga I2C to Bcc I2C Bridge
72
On-Board Indicators
73
Table 7-19: Board-Status and User Leds
73
User FPGA Pinning
74
User FPGA Reset Inputs
74
Table 7-20: Tpce636 User On-Board Indicators
74
Table 7-21: User Fpga Reset Inputs
74
Design Help
75
Board Reference Design
75
O Interfaces
76
Front I/O - ADC Analog Input Level
76
Table 9-1 : Differential Input Voltage Ranges
76
Front I/O - Analog Output Level
77
Back I/O Interface
77
Figure 9-1 : Dac Output Interface
77
Table 9-2 : Dac Electrical Interface
77
O Description
78
Overview
78
Front I/O Connector (X1)
79
Connector Type
79
Pin Assignment
79
Table 10-1 : Front I/O Connector
79
Table 10-2: Pin Assignment Front Panel I/O Connector
80
Digital Back I/O Connector (X7)
81
Connector Type
81
Pin Assignment
81
Table 10-3 : Back I/O Connector
81
Figure 10-1 : Pin Assignment Back I/O Connector Tpce636
82
MGT Back I/O Connector (X8/X9)
83
Connector Type
83
Pin Assignment
83
Figure 10-2 : Firefly Back I/O Connector Tpce636
83
Figure 10-3 : Pin Assignment Firefly Back I/O Connector Tpce636
83
Connector Type
84
Pin Assignment
84
Figure 10-4 : Firefly Back I/O Connector Tpce636
84
Figure 10-5 : Pin Assignment Firefly Back I/O Connector Tpce636
84
FPGA JTAG Header (X5)
85
Connector Type
85
Pin Assignment
85
Figure 10-6 Jtag Header Tpce636
85
Table 10-4: Pin Assignment Jtag Header
85
FPGA USB Connector (X2)
86
Connector Type
86
Pin Assignment
86
Figure 10-7 Fpga Usb Connector Tpce636
86
Table 10-5: Pin Assignment Usb Type C Connector
86

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Tews Technologies TPCE636 User Manual (104 pages)

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