Philips SC16C2550 Manual page 35

Philips Semiconductors
RX
RXRDY
IOR
Fig 12. Receive ready timing in non-FIFO mode.
RX
RXRDY
IOR
Fig 13. Receive ready timing in FIFO mode.
9397 750 11621
Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
START
BIT
DATA BITS (5–8)
D0 D1 D2
START
BIT
DATA BITS (5–8)
D0 D1 D2
Rev. 03 — 19 June 2003
D3 D4 D5 D6 D7
D3 D4 D5 D6 D7
SC16C2550
encoder/decoder
NEXT
DATA
PARITY STOP START
BIT BIT BIT
t
25d
ACTIVE
DATA
READY
t
26d
ACTIVE
002aaa114
PARITY STOP
BIT BIT
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t
25d
ACTIVE
DATA
READY
t
26d
ACTIVE
002aaa115
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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