Philips SC16C2550 Manual page 15

Philips Semiconductors
SC16C2550
D0–D7
IOR
IOW
RESET
A0–A2
CSA, CSB
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
Fig 6. Internal loop-back mode diagram.
9397 750 11621
Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERRUPT
CONTROL
LOGIC
Rev. 03 — 19 June 2003
TRANSMIT TRANSMIT
FIFO SHIFT
REGISTER REGISTER
RECEIVE RECEIVE
FIFO SHIFT
REGISTER REGISTER
MODEM
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
XTAL1 XTAL2
SC16C2550
encoder/decoder
TXA, TXB
MCR[4] = 1
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
DSRA, DSRB
(OP1A, OP1B)
RIA, RIB
(OP2A, OP2B)
CDA, CDB
002aaa120
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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