Timing Diagrams - Philips SC16C2550 Manual

Philips Semiconductors

10.1 Timing diagrams

A0–A2
t
CSx
IOW
D0–D7
Fig 7. General write timing.
A0–A2
t
CSx
IOR
D0–D7
Fig 8. General read timing.
9397 750 11621
Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
VALID
ADDRESS
6s
ACTIVE
t
13d
t
13w
ACTIVE
t
16s
DATA
VALID
ADDRESS
6s
ACTIVE
t
7d
t
7w
ACTIVE
t
12d
DATA
Rev. 03 — 19 June 2003
t
6h
t
13h
t
15d
t
16h
t
6h
t
7h
t
9d
t
12h
SC16C2550
encoder/decoder
002aaa109
002aaa110
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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