Line Control Register (Lcr) - Philips SC16C2550 Manual

Philips Semiconductors

7.5 Line Control Register (LCR)

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Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Table 12: Interrupt Status Register bits description
Bit Symbol
7-6 ISR[7-6]
5-4 ISR[5-4]
3-1 ISR[3-1]
0 ISR[0]
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 13: Line Control Register bits description
Bit Symbol
7 LCR[7]
6 LCR[6]
5-3 LCR[5-3]
2 LCR[2]
1-0 LCR[1-0]
Rev. 03 — 19 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550 mode.
Logic 0 or cleared = default condition.
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
Logic 0 or cleared = default condition.
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
Description
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Logic 0 or cleared = default condition.
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Logic 0 or cleared = default condition.
SC16C2550
encoder/decoder
Table
Table 14).
Table
Table 16).
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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