Register Descriptions - Philips SC16C2550 Manual

Philips Semiconductors

7. Register descriptions

Table 7: SC16C2550 internal registers
Shaded bits are only accessible when EFR[4] is set.
A2 A1 A0 Register Default
[2]
General Register Set
0 0 0 RHR
0 0 0 THR
0 0 1 IER
0 1 0 FCR
0 1 0 ISR
0 1 1 LCR
1 0 0 MCR
1 0 1 LSR
1 1 0 MSR
1 1 1 SPR
[3]
Special Register Set
0 0 0 DLL
0 0 1 DLM
[4]
Enhanced Register Set
0 1 0 EFR
1 0 0 Xon-1
1 0 1 Xon-2
1 1 0 Xoff-1
1 1 1 Xoff-2
[1] The value shown in represents the register's initialized HEX value; X = n/a.
[2] Accessible only when LCR[7] is logic 0.
[3] Baud rate registers accessible only when LCR[7] is logic 1.
[4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to 'BF
9397 750 11621
Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Table 7 details the assigned bit functions for the SC16C2550 internal registers. The
assigned bit functions are more fully defined in
[1]
Bit 7 Bit 6
XX bit 7 bit 6
XX bit 7 bit 6
00 CTS RTS
interrupt interrupt
00 RCVR RCVR
trigger trigger
(MSB) (LSB)
01 FIFOs FIFOs
enabled enabled
00 divisor set break set parity even
latch
enable
00 0 IR
enable
60 FIFO THR and
data TSR
error empty
X0 CD RI
FF bit 7 bit 6
XX bit 7 bit 6
XX bit 15 bit 14
00 Auto Auto
CTS RTS
00 bit 7 bit 6
00 bit 15 bit 14
00 bit 7 bit 6
00 bit 15 bit 14
Rev. 03 — 19 June 2003
Section 7.1
Bit 5 Bit 4 Bit 3
bit 5 bit 4 bit 3
bit 5 bit 4 bit 3
Xoff Sleep modem
interrupt mode status
interrupt
reserved reserved DMA
0 0 mode
select
INT INT INT
priority priority priority
bit 4 bit 3 bit 2
parity
parity enable
0 loop back OP2/INT
enable
THR break framing
empty interrupt error
∆CD
DSR CTS
bit 5 bit 4 bit 3
bit 5 bit 4 bit 3
bit 13 bit 12 bit 11
Special Enable Cont-3
char. IER[4-7], Tx, Rx
select ISR[4,5], Control
FCR[4,5],
MCR[5-7]
bit 5 bit 4 bit 3
bit 13 bit 12 bit 11
bit 5 bit 4 bit 3
bit 13 bit 12 bit 11
SC16C2550
encoder/decoder
through Section
Bit 2 Bit 1
bit 2 bit 1
bit 2 bit 1
receive transmit
line holding
status register
interrupt interrupt
XMIT RCVR
FIFO FIFO
reset reset
INT INT
priority priority
bit 1 bit 0
stop bits word
length
bit 1
(OP1) RTS
parity overrun
error error
∆RI ∆DSR
bit 2 bit 1
bit 2 bit 1
bit 10 bit 9
Cont-2 Cont-1
Tx, Rx Tx, Rx
Control Control
bit 2 bit 1
bit 10 bit 9
bit 2 bit 1
bit 10 bit 9
'.
Hex
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.11.
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
∆CTS
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
bit 0
bit 8
bit 0
bit 8
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