Transmit (Thr) And Receive (Rhr) Holding Registers; Interrupt Enable Register (Ier) - Philips SC16C2550 Manual

Philips Semiconductors

7.1 Transmit (THR) and Receive (RHR) Holding Registers

7.2 Interrupt Enable Register (IER)

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Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16× clock rate. After 7-
clocks, the start bit time should be shifted to the center of the start bit. At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. Receiver status
codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 8: Interrupt Enable Register bits description
Bit Symbol
7 IER[7]
6 IER[6]
5 IER[5]
4 IER[4]
3 IER[3]
Rev. 03 — 19 June 2003
Description
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C2550 issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C2550 issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff interrupt.
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode.
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
SC16C2550
encoder/decoder
1
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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