Dma Operation; Loop-Back Mode - Philips SC16C2550 Manual

Philips Semiconductors

6.9 DMA operation

6.10 Loop-back mode

9397 750 11621
Product data
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Table 6: Baud rate generator programming table using a 1.8432 MHz clock
Output Output
16 × clock divisor
baud rate
(decimal)
50 2304
75 1536
110 1047
150 768
300 384
600 192
1200 96
2400 48
3600 32
4800 24
7200 16
9600 12
19.2 k 6
38.4 k 3
57.6 k 2
115.2 k 1
The SC16C2550 FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[5,6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs
in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and
the DMA mode is de-activated (DMA Mode 0), the SC16C2550 activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the receive trigger level and
the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output
pin when characters in the transmit FIFO is below 16, or the characters in the receive
FIFOs are above the receive trigger level.
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
Rev. 03 — 19 June 2003
Output DLM
16 × clock divisor
program value
(HEX) (HEX)
900 09
600 06
417 04
300 03
180 01
C0 00
60 00
30 00
20 00
18 00
10 00
0C 00
06 00
03 00
02 00
01 00
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2550
encoder/decoder
DLL
program value
(HEX)
00
00
17
00
80
C0
60
30
20
18
10
0C
06
03
02
01
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