Motorola M68360QUADS-040 User Manual page 3

3.4 Programming the slave QUICC
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
3.4.19
3.4.20
3.4.21
3.4.22
3.4.23
3.4.24
3.4.25
3.4.26
3.4.27
4 - FUNCTIONAL DESCRIPTION
4.1 INTRODUCTION
4.2 Master MC68EC040
4.2.1
4.2.2
4.3 Interrupts on the M68360QUADS-040
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4 Bus Arbitration
4.5 System Utilities
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.6 Clock Generator
4.7 Flash PROM
4.8 Bursting SRAM
4.9 EEPROM
4.10 DRAM
4.11 Slave QUICC
4.11.1
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Module Base Address Register
Module Configuration Register
CLKO Control Register
PLL Control Register
Port E Pin Assignment Register
System Protection Control
Global Memory Register
Base Register 0 and Option Register 0
Base Register 1 and Option Register 1
Base Register 2 and Option Register 2
Base Register 3 and Option Register 3
Base Register 4 and Option Register 4
Base Register 5 and Option Register 5
Base Register 6 and Option Register 6
Base Register 7 and Option Register 7
Port A Open Drain Register
Port A Data Register
Port A Data Direction Register
Port A Pin Assignment Register
Port B Open Drain Register
Port B Data Register
Port B Data Direction Register
Port B Pin Assignment Register
Port C Data Register
Port C Data Direction Register
Port C Pin Assignment Register
Port C Special Options Register
RESET for the 68EC040 & the QUICC
Utilizing the MC68EC040 Data Cache
ABORT Push-button
Host - NMI
Hardware-Breakpoint Interrupt
Parity Error Interrupt
Host Request / Acknowledge Interrupt
Breakpoints Generator
Bus Monitor
Spurious Interrupt Monitor
software Watch-Dog
Periodic Interval Timer - PIT
DRAM Controller
For More Information On This Product,
Go to: www.freescale.com
M68360QUADS-040 - User's Manual
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Draft 1.0