I/O Buffer Circuit; Display Data Latch Circuit - Epson S1D15722 Series Technical Manual

6. FUNCTIONAL DESCRIPTION

6.2.5 I/O Buffer Circuit

Bi-directional buffer for reading or writing display data RAM from the side of MPU. Since read or write of
display data RAM from the side of MPU is controlled independently of data output from the display data RAM
to the display data clutch circuit, an asynchronous access made to the display data RAM during crystal liquid
display does not have an adverse effect on display, including flickering.

6.2.6 Display Data Latch Circuit

The display data latch circuit is a latch for temporarily storing data to be output to the liquid crystal drive
circuit from the display data RAM. Since the display normal/inverted, display ON/OFF, and display full
lighting ON/OFF commands control data in this latch, data in the display data RAM will not change.
18 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)