Texas Instruments UCD90240EVM-704 User Manual page 7

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Connectors Pins
J6
J7
J8
J9
J10
SLVUAF3A – March 2015 – Revised March 2015
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Table 2. Connector Definition (continued)
Name
1 EN17
2 EN18
3 EN19
4 EN20
5 EN21
6 EN22
7 EN23
8 EN24
1 LGPO1
2 LGPO2
3 LGPO3
4 LGPO4
5 LGPO5
6 LGPO6
7 LGPO7
8 LGPO8
1 LGPO9
2 LGPO10
3 LGPO11
4 LGPO12
5 GPIO1
6 GPIO2
7 GPIO3
8 GPIO4
1 PMBUS_ADDR0
2 PMBUS_ADDR1
3 PMBUS_ADDR2
4 SYNC_CLOCK
5 GPIO21
6 GPIO22
7 GPIO23
8 GPIO24
1 GPIO13
2 GPIO14
3 GPIO15
4 GPIO16
5 GPIO17
6 GPIO18
7 GPIO19
8 GPIO20
Copyright © 2015, Texas Instruments Incorporated
Description
Rail enable output
Rail enable output
Rail enable output
Rail enable output
Rail enable output
Rail enable output
Rail enable output
Rail enable output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
Logic GPO output
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
PMBus address pin
PMBus address pin
PMBus address pin
Sync Clock pin
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
UCD90240EVM-704 24-Rail Sequencer Development Board
Test Setup
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