Sdmspeed() Instruction; Bit Period Values - Campbell SDM-AO4A Product Manual

7.1.2 SDMSpeed() Instruction

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SDMAO4AOption: The SDMAO4AOption parameter is used to set the
operating mode for the SDMAO4A.
Option Code Description
0 Power down
1 5V synchronous
2 5V sequential
3 10V synchronous
4 10V sequential
In the synchronous mode, all channels are set at the same time. This mode is
slower since for large changes in voltage it may take multiple charging cycles
to arrive at the final voltage. The steps occur at 5 ms intervals, thus, for a 10V
step it may take up to three charge cycles (or 15 ms) to settle to the 16-bit level.
In sequential mode, the channels are set sequentially. The output signal can
take from 600 usecs to 1 ms (worst case) to settle to 16-bit resolution with a
10V step change. The four outputs then update 1 ms apart.
The SDMSpeed() instruction is used to change the bit period that the data
logger uses to clock the SDM data. Slowing down the clock rate may be
necessary when long cable lengths are used to connect the data logger and
SDM devices.
The syntax of this instruction is as follows:
SDMSpeed (BitPeriod)
The BitPeriod argument can be an integer or a variable. If the SDMSpeed()
instruction is not in the program, a default bit period is used. If 0 is used for the
argument, the minimum allowable bit period is used. TABLE
default, minimum allowable, and maximum bit period for each of our CRBasic
data loggers.
TABLE 7-1. Bit Period Values
Default
Data Logger Bit Period
CR6, CR1000X 28.8 μsec
CR3000
26.04 µsec
CR800, CR850 26.04 µsec
CR1000 26.04 µsec
The equation used to calculate the bit rate depends on the data logger used. The
data logger will round down to the next faster bit rate.
SDM-AO4A Four-Channel Analog Output
7-1
Minimum
Allowable Maximum
Bit Period Bit Period
10 μsec 1 msec
2.2 msec
8.68 µsec
8.68 µsec 2.2 msec
8.68 µsec 2.2 msec
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