Available Processor Speeds - IBM System p5 550 Technical Overview And Introduction

Figure 2-5 The p5-550 POWER5+ 2.1 GHz DCM with DDR2 memory socket layout view
The storage structure for the POWER5+ processor is a distributed memory architecture that
provides high-memory bandwidth, although each processor can address all memory and
sees a single shared memory resource. They are interfaced to eight memory slots, controlled
by two SMI-II chips, which are located in close physical proximity to the processor modules.
I/O connects to the p5-550 processor module using the GX+ bus. The processor module
provides a single GX+ bus. The GX+ bus provides an interface to I/O devices through the
RIO-2 connections.
The theoretical maximum throughput of the L3 cache is 16 byte read, 16 byte write at a bus
frequency of 1.05 GHz (based on a 2.1 GHz processor clock), which equates to 33600 MBps
or 33.6 GBps. Table 2-3 on page 33 provides a summary of the cumulative throughput rates
for memory, cache, and I/O for the p5-550 and p5-550Q.

2.2.3 Available processor speeds

Table 2-1 describes the available processor capacities and speeds for the p5-550 and
p5-550Q systems.
Table 2-1 The p5-550 and p5-550Q available processor capacities and speeds
Capacities
2-core
4-core
8-core
To determine the processor characteristics, use one of the following commands:
lsattr -El procX
In this command, X is the number of the processor. For example, proc0 is the first
processor in the system. The output from the command is similar to the following output
(False, as used in this output, signifies that the value cannot be changed through an
AIX 5L command interface):
frequency 1498500000
smt_enabled true
smt_threads 2
state enable
type powerPC_POWER5
DIMM DIMM
DIMM DIMM
DIMM DIMM
DIMM DIMM
2 x 8 B 2 x 8 B
@528 MHz @528 MHz
DIMM DIMM
DIMM DIMM
DIMM DIMM
1056 MHz 1056 MHz
2 x 8 B for read 2 x 8 B for read
DIMM DIMM
2 x 2 B for write 2 x 2 B for write
p5-550 @ 1.65, 1.9, or 2.1 GHz
Yes
Yes
No
Processor Speed
Processor SMT enabled False
Processor SMT threads False
Processor state
Processor type
DCM DCM
POWER5+ POWER5+ POWER5+
core core core
2.1 GHz 2.1 GHz 2.1 GHz
2x16B 2x16B
@1.05 GHz @1.05 GHz
36 MB 36 MB
L3 L3
1.9 MB Shared 1.9 MB Shared
L3 cache L3 cache
Ctrl Ctrl
L2 cache L2 cache
Mem Mem
Enhanced distributed switch Enhanced distributed switch
Ctrl Ctrl
p5-550Q @ 1.5 or 1.65 GHz
No
Yes
Yes
False
False
False
Chapter 2. Architecture and technical overview
GX+ GX+ GX+ GX+
Bus Bus
Ctrl Ctrl
POWER5+ POWER5+ POWER5+
core core core
2.1 GHz 2.1 GHz 2.1 GHz
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