HP X Class 500/550MHz Reference Manual page 40

System Board
Chipset
Main Memory Controller
The main memory controller supports four DIMM sockets; Mem 1, Mem 2, Mem 3 and
Mem 4. Each socket can host a 168-pin SDRAM memory module, running at 100 MHz, and
can support unbuffered and registered memory modules. Each DIMM socket is connected
to the SMBus.
The Intel 440GX AGP set provides DIMM plug-and-play support via the Serial Presence
Detect (SPD) mechanism using the SMBus interface. The Host Bridge provides optional
data integrity features including ECC in the memory array. During reads from DRAM, the
Host Bridge provides error checking and correction of the data. The Host Bridge supports
multiple-bit error detection and single-bit error correction when the ECC mode is enabled
and single/multi-bit error detection when correction is disabled. During writes to the
DRAM, the Host Bridge generates ECC for the data on a QWord basis. Partial QWord
writes require a read-modify-write cycle when ECC is enabled.
The memory bus is 72-bits wide, comprised of 64 bits of data and 8 bits of ECC. Refer to the
section "Main Memory Bus" in this chapter for more detail on the main memory.
Read/Write Buffer
The Host Bridge defines a data buffering scheme to support the required level of
concurrent operations and provide adequate sustained bandwidth between the DRAM
subsystem and all other system interfaces (CPU, AGP and PCI).
System Clocking
The Host Bridge operates the host interface at 100 MHz, PCI at 33 MHz and AGP at
66/133 MHz. Coupling between all interfaces and internal logic is done in a synchronous
manner. The clocking scheme uses an external clock synthesizer (which produces reference
clocks for the host, AGP and PCI interfaces).
I/O APIC
I/O APIC is used to support dual processors as well as enhanced interrupt processing in
the single processor environment. The Host Bridge supports an external status output
that can be used to control synchronization of interrupts in configurations that use PIIX4E
with stand-alone I/O APIC components.
40 Chapter 2