Chipset; Host Bridge/Controller (82443Gx) - HP X Class 500/550MHz Reference Manual

Chipset

The Intel® 440GX AGPset chipset is comprised of the 82443GX Host Bridge/Controller
and, the 82371EB (PIIX4E) chip, which is a highly integrated version of the Intel PCI-ISA
bridge family for the I/O subsystem.
• The Host Bridge, also referred to as the North Bridge, is the bridge between four buses:
the Front Side Bus (FSB), the main memory (SDRAM) bus, the PCI bus and the AGP
(graphic) bus.
• The PIIX4E chip, also referred to as the South Bridge, is the bridge between three
buses: the PCI bus, the SMBus and the ISA bus. In addition, it contains the IDE
controller, USB controller and Power Management logic, Interrupt controller, Real Time
Clock (RTC) and CMOS. The table "PIIX4E (82371EB)" in this chapter details the
PIIX4E chip features.

Host Bridge/Controller (82443GX)

The Host Bridge/Controller is contained in a 492-pin Ball Grid Array (BGA) package. The
following table shows the features that are available in the Host Bridge/Controller.
Table 2-2. Features Available in the Host Bridge/Controller
Feature
Processor/Host Bus Support
• Optimized for Pentium® processor at: 100
MHz system bus frequency.
• Supports full Symmetric Multiprocessor
(SMP) Protocol for up to two processors; I/O
APIC related buffer management support
(WSC# signal).
• In-order transaction and dynamic deferred
transaction support.
• Desktop optimized
technology (gated
reduced power).
Chapter 2
GTL+ bus driver
GTL+ receivers for
Feature
AGP Interface
• Supports single
(AGP-66/133 3.3V
device).
• AGP Specifications Rev. 1.0 compliant.
• AGP-data/transaction
arbitration mechanism.
• AGP side-band interface for efficient request
pipelining without interfering with the data
streams.
• AGP-specific data buffering.
• Supports concurrent CPU, AGP and PCI
transactions to main memory.
• AGP high-priority transactions ("expedite")
support.
System Board
Chipset
AGP-compliant device
flow optimized
37