Architectural View - HP X Class 500/550MHz Reference Manual

Architectural View

Figure 2-2. Architectural View
On each processor there
is a SMBus EEPROM
and SMBus Thermal
SEC car-
Address (32)
Control
Data (64)
Graphics
Local Mem-
Video
BIOS
PCI Bus
(32 bit, 33
MHz)
133 MB/sec.
Internal
DMA
Connector
ISA Bus
(16 bit, 8.33 MHz)
29F002T
1
The graphics board depends on the model of Personal Workstation.
Chapter 2
Intel Pentium III
Xeon Processor with L2
cache memory
AGP
AGP Bus
Graph-
(32-bit, 66 MHz
ics
(2X), 528 MB/sec
data transfer rate)
Adaptec
AIC7880
16-bit SCSI
Controller
Internal 16-bit
SCSI Connec-
IDE
USB 1
USB 2
Intel 82093 IO APIC
Two
external interrupt con-
SMBus
Intel Pentium III
Xeon Processor
(optional second proces-
sor) with L2 cache mem-
440GX
Memory Bus
Host Bridge
(72-bit ECC
82443GX
100 MHz, 800
MB/ sec data
transfer rate)
PCI Bus
Interface
SMBus
PCI/ISA
Control-
Bridge
(PIIX4E)
MaxiLife
DMA
Monitor-
Control-
ing Chip
IDE Interrupt
Control- Control-
2 x USB
ISA Bus
Control-
Interface
AD-1816
Super I/O
Audio
NS 97317
System Board
Architectural View
SEC cartridge
Host (also called
FSB) Bus (64 bit,
100 MHz, 800
MB/sec data
transfer rate)
Main Memory
4 DIMMS
(Serial Pres-
ence Detect)
PCI Slots
CK4
Clock
D
Clock
SMBus
LCD Serial
EEPR
ISA Slot
31