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m (S)
FOR ORDERRING.
T,AND MAY BE
S PREPARED.
C7508
0.1
30
29
28
27 26
C7514
0.1
R7523
220
IR
25
VREF+[5V]
24
DI_P_ON_H
23
AFC
22
BS_LEVEL
21
L123_SWIDE2
20
L123_SWIDE
19
R7513
100
KEY3
18
R7514
100
KEY2
17
R7515
100
KEY1
16
R7516
MMOD
15
R7505
0
4700
32KOUT
14
32KIN
13
GND
12
20MHZIN
11
20MHZOUT
10
R7504
0
VDD[5V]
9
X_RESET
8
JC_PON_H
7
TBUS_CLK
6
TBUS_RXD
5
TBUS_TXD
4
3
FL_ON_L
WRITE_RX
2
WRITE_TX
1
96 97 98
99
100
TL7501
O
P
3
70
0.01
C7501
0.01
C7502
0.01
C7503
H0A327200108
C7513
15P
X7502
C7512
22P
H0D100500006
X7501
C7509 0.1
C7511 18P
C7510
18P
10K
R7544
10K
R7543
Q
R
S
TW7501
VWJ0795=5
KEY1
KEY2
IR
KEY3
DI_PON_H
CL7524
AFC
SYS_PFAIL
L12_SWIDE_A
JC_PON
R7517 270K
SCLK
SBMTP
TL7507
SBPTM
FL_ON_L
UARTM2P
UARTP2M
XFWE
10K
R7534
T
U
V
W
4
B7501
CR2354-1GUF
N4BCT50A0005
or
RESET
R7525
IC7503
0
C0EBE0000457
C7520 0.1[KB]
R7535
10K
R7536
4700
Q7503
DMR-ES45VP/ES46VP
Syscon/Servo/
Timer(1/4) Section
X
(Main P.C.B.(3/4))
Schematic Diagram(S)
5
1
E
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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