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5.4
Electrical Characteristics
TYP operating conditions are T
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
I
Supply current in power down mode 1
PD1
Supply current in power down mode 2
I
PD2
(sleep mode)
I
Supply current in standby mode
STBY
Supply current without antenna driver
I
ON1
current
I
Supply current in TX (half power)
ON2
I
Supply current in TX (full power)
ON3
V
Power-on reset voltage
POR
V
Bandgap voltage (pin 11)
BG
Regulated output voltage for analog
V
DD_A
circuitry (pin 1)
V
Regulated supply for external circuitry
DD_X
I
Maximum output current of VDD_X
VDD_Xmax
R
Antenna driver output resistance
RFOUT
R
RX_IN1 and RX_IN2 input resistance
RFIN
Maximum RF input voltage at RX_IN1
V
RF_INmax
or RX_IN2
Minimum RF input voltage at RX_IN1
V
RF_INmin
or RX_IN2 (input sensitivity)
f
SYS_CLK frequency
SYS_CLK
f
Carrier frequency
C
t
Crystal run-in time
CRYSTAL
f
Maximum DATA_CLK frequency
D_CLKmax
V
Input voltage, logic low
IL
V
Input voltage threshold, logic high
IH
R
Output resistance, I/O_0 to I/O_7
OUT
R
Output resistance R
SYS_CLK
(1) Antenna driver output resistance
(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1
(3) Depending on the crystal parameters and components
(4) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω (12-ns time constant when 30-pF load is used).
Copyright © 2011–2020, Texas Instruments Incorporated
= 25°C, V
= 5 V, full-power mode (unless otherwise noted)
A
IN
All building blocks disabled, including supply-
voltage regulators; measured after 500-ms
settling time (EN = 0, EN2 = 0)
The SYS_CLK generator and VDD_X remain
active to support external circuitry, measured
after 100-ms settling time (EN = 0, EN2 = 1)
Oscillator running, supply-voltage regulators in
low-consumption mode (EN = 1, EN2 = x)
Oscillator, regulators, RX, and AGC are active,
TX is off
Oscillator, regulators, RX, AGC, and TX
active, P
OUT
Oscillator, regulators, RX, AGC, and TX
active, P
OUT
Input voltage at VIN
Internal analog reference voltage
V
= 5 V
IN
Output voltage pin 32, V
Output current pin 32, V
Half-power mode, V
(1)
Full-power mode, V
V
RF_INmax
f
SUBCARRIER
(2)
f
SUBCARRIER
In power mode 2, EN = 0, EN2 = 1
Defined by external crystal
Time until oscillator stable bit is set (register
(3)
0x0F)
Depends on capacitive load on the I/O lines,
(4)
recommendation is 2 MHz
I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,
EN2
I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,
EN2
SYS_CLK
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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
TEST CONDITIONS
= 100 mW
= 200 mW
= 5 V
IN
= 5 V
IN
= 2.7 V to 5.5 V
IN
= 2.7 V to 5.5 V
IN
should not exceed VIN
= 424 kHz
= 848 kHz
(4)
TRF7963A
TRF7963A
MIN
TYP
MAX
UNIT
<0.5
5
µA
120
200
µA
1.9
3.5
mA
10.5
14
mA
70
78
mA
130
170
mA
1.4
2
2.6
V
1.5
1.6
1.7
V
3.1
3.5
3.8
V
3.1
3.4
3.8
V
20
mA
8
12
Ω
4
6
4
10
20
kΩ
3.5
V
pp
1.4
2.5
mV
2.1
3
25
60
120
kHz
13.56
MHz
5
ms
2
4
10
MHz
0.2 ×
V
V
DD_I/O
0.8 ×
V
V
DD_I/O
500
800
Ω
200
400
Ω
Specifications
pp
9
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