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TPSM63610
SLVSGU1 – NOVEMBER 2022
(2)
Under no conditions should the output voltage be allowed to fall below zero volts.
7.4 Thermal Information
R
Junction-to-ambient thermal resistance (TPSM63610EVM)
θJA
R
Junction-to-ambient thermal resistance (JESD 51-7)
θJA
R
Junction-to-case (top) thermal resistance
θJC(top)
R
Junction-to-board thermal resistance
θJB
Ψ
Junction-to-top characterization parameter
JT
Ψ
Junction-to-board characterization parameter
JB
R
Junction-to-case (bottom) thermal resistance
θJC(bot)
(1)
For more information about traditional and new thermal metrics, see the
report.
(2)
The value of R
given in this table is only valid for comparison with other packages and can not be used for design purposes.
ΘJA
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For example, the EVM R
Thermal Design and Layout
(3)
Refer to the
EVM User's Guide
Design and Layout
section.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise noted.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at T
conditions apply: V
= 12. VIN1 shorted to VIN2 = V
IN
PARAMETER
SUPPLY VOLTAGE (VIN PIN)
V
Minimum operating input voltage
IN
V
Minimum voltage hysteresis
IN_OP_H
Non-switching input current; measured
I
Q
(3)
at VIN pin
Shutdown quiescent current; measured
I
SD
at VIN pin
I
Current into BIAS pin (not switching)
B
ENABLE (EN PIN)
V
Enable input-threshold voltage - rising
EN
V
Enable threshold hysteresis
EN_HYST
V
Enable Wake-up threshold
EN_WAKE
I
Enable pin input current
EN
INTERNAL LDO (VCC PIN)
V
Internal VCC voltage
CC
V
voltage at which Internal VCC under
IN
V
CC_UVLO
voltage lock-out is released
Internal VCC under voltage lock-out
V
CC_UVLO_HYST
hysteresis
VOLTAGE REFERENCE (FB PIN)
6
Submit Document Feedback
(1)
THERMAL METRIC
section.
for board layout and additional information. For thermal design information please see the
= 25°C, and are provided for reference purposes only. Unless otherwise stated the following
J
IN
Needed to start up
Once Operating
V
V
V
Enabled
V
V
V
V
I
VCC
Hysteresis below V
Product Folder Links:
(3)
(2)
Semiconductor and IC Package Thermal Metrics
= 21.6 °C/W. For design information please see the
ΘJA
. V
is output set point.
OUT
TEST CONDITIONS
= +5%, V
= 5 V
FB
BIAS
= 0 V, V
= 12 V
EN
IN
= +5%, V
= 5 V, Auto Mode
FB
BIAS
rising
EN
= V
= 12 V
IN
EN
= 0V
BIAS
= 3.3 V, 20 mA
BIAS
= 0A
CC_UVLO
TPSM63610
www.ti.com
TPSM636XX
RDF
22 PINS
18
25
12.8
7.4
0.7
7.2
3.6
application
Thermal
MIN
TYP
MAX
3.7
3
1
0.5
10
0.57
7.5
18.5
26
1.0
1.263
1.365
0.1
0.35
0.5
0.4
1.5
50
3.4
3.2
3.75
1.2
Copyright © 2022 Texas Instruments Incorporated
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
UNIT
V
V
V
µA
µA
µA
V
V
V
nA
V
V
V
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