Texas Instruments TRF7963A Manual page 7

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TERMINAL
TYPE
NO. NAME
20 I/O_3
21 I/O_4
22 I/O_5
23 I/O_6
24 I/O_7
25 EN2
26 DATA_CLK
27 SYS_CLK OUT
28 EN
29 VSS_D SUP
30 OSC_OUT OUT
31 OSC_IN
32 VDD_X OUT
PAD PAD SUP
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Table 4-1. Signal Descriptions (continued)
(1)
BID I/O pin for parallel communication
I/O pin for parallel communication
BID
Slave select signal in SPI mode
I/O pin for parallel communication
BID
Data clock output in direct mode 1
I/O pin for parallel communication
BID MISO for serial communication (SPI)
Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
I/O pin for parallel communication.
BID
MOSI for serial communication (SPI)
Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power
INP
down mode 2 (for example, to supply the MCU).
INP Data clock input for MCU communication (parallel and serial)
If EN = 1 (EN2 = don't care) the system clock for the MCU is configured with register 0x09 (off,
3.39 MHz, 6.78 MHz, or 13.56 MHz).
If EN = 0 and EN2 = 1, the system clock is set to 60 kHz.
INP Chip enable input (if EN = 0, then the chip is in sleep or power-down mode)
Negative supply for internal digital circuits
Crystal or oscillator output
INP Crystal or oscillator input
Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an
MCU)
Chip substrate ground
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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
DESCRIPTION
Terminal Configuration and Functions
TRF7963A
TRF7963A
7