Ddr3 Cha So-Dimm_0 - Clevo P770ZM Service Manual

Schematic Diagrams

DDR3 CHA SO-DIMM_0

Channel A SO-DIMM 0[RAM1]
D
Sheet 7 of 57
DDR3 CHA SO-
DIMM _0
C
B
A
VTT_MEM
B - 8 DDR3 CHA SO-DIMM_0
5 4
STANDARD TYPE
JDIMM1A JDIMM1A
4,8 M_A_A[15:0]
M_A_A0 98
A0
97
M_A_A1
A1
M_A_A2 96
A2
M_A_A3 95
A3
M_A_A4 92
A4
M_A_A5 91
A5
90
M_A_A6
A6
M_A_A7 86
A7
89
M_A_A8
A8
M_A_A9 85
A9
M_A_A10 107
A10/AP
84
M_A_A11
A11
M_A_A12 83
A12/BC#
119
M_A_A13
A13
M_A_A14 80
A14
M_A_A15 78
A15
109
4,8 M_A_BS0 BA0
108
4,8 M_A_BS1
BA1
79
4,8 M_A_BS2
BA2
114
4 M_A_CS#0 S0#
121
4 M_A_CS#1
S1#
101
4 M_A_CLK_DDR0 CK0
103
4 M_A_CLK_DDR#0
CK0#
102
4 M_A_CLK_DDR1
CK1
104
4 M_A_CLK_DDR#1 CK1#
73
4 M_A_CKE0
CKE0
74
4 M_A_CKE1 CKE1
115
4,8 M_A_CAS#
CAS#
110
4,8 M_A_RAS#
RAS#
113
4,8 M_A_WE# WE#
197
CHA_SA0_DIM0
SA0
CHA_SA1_DIM0 201
SA1
202
10,17,27,28,36,8,9 SMB_CLK
SCL
200
10,17,27,28,36,8,9 SMB_DATA SDA
116
4 M_A_ODT0
ODT0
120
4 M_A_ODT1 ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
4,8 M_A_DQS[7:0]
12
M_A_DQS0
DQS0
M_A_DQS1 29
DQS1
47
M_A_DQS2
DQS2
M_A_DQS3 64
DQS3
M_A_DQS4 137
DQS4
M_A_DQS5 154
DQS5
M_A_DQS6 171
DQS6
188
M_A_DQS7
DQS7
4,8 M_A_DQS#[7:0]
M_A_DQS#0 10
DQS0#
M_A_DQS#1 27
DQS1#
M_A_DQS#2 45
DQS2#
62
M_A_DQS#3
DQS3#
M_A_DQS#4 135
152 DQS4#
M_A_DQS#5
DQS5#
M_A_DQS#6 169
DQS6#
M_A_DQS#7 186
DQS7#
DS2SK-20401 -TR4B DS2SK-20401 -TR4B
VDDQ
1.56A x4 (6.24 A ) 6-86-24204-043
C569 C569 C590 C590 + + C596 C596 C607 C607
+ + + +
330uF_2.5V_12m_6.6*6.6*4.2 330uF_2.5V_12m_6.6*6.6*4.2 330uF_2.5V_12m_6.6*6.6*4.2 330uF_2.5V_12m_6.6*6.6*4.2 220u_6.3V_6.3*6.3*4.2 220u_6.3V_6.3*6.3*4.2 10u_6.3V_X5R_06 10u_6.3V_X5R_06
VDDQ
C608 C608 C601 C601 C624 C624 C617 C617 C623 C623 C622 C622
0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04
C626 C626 C671 C671 C675 C675 C633 C633 C638 C638
10u_6.3V_X5R_06 10u_6.3V_X5R_06 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
5 4
3
M_A_DQ[63:0] 4,8
5 M_A_DQ0
DQ0
7
M_A_DQ1
DQ1
15 M_A_DQ2
DQ2
17 M_A_DQ3
DQ3
4 M_A_DQ4
DQ4
6 M_A_DQ5
DQ5
16
M_A_DQ6
DQ6
18 M_A_DQ7
DQ7
21
M_A_DQ8
DQ8
23 M_A_DQ9
DQ9
33 M_A_DQ10
DQ10
35
M_A_DQ11
DQ11
22 M_A_DQ12
DQ12
24
M_A_DQ13
DQ13
34 M_A_DQ14
DQ14
36 M_A_DQ15
DQ15
39
M_A_DQ16
DQ16
41 M_A_DQ17
DQ17
51
M_A_DQ18
DQ18
53 M_A_DQ19
DQ19
40 M_A_DQ20
DQ20
42
M_A_DQ21
DQ21
50 M_A_DQ22
DQ22
52
M_A_DQ23
DQ23
57 M_A_DQ24
DQ24
59 M_A_DQ25
DQ25
67 3.3VS
M_A_DQ26
DQ26
69 M_A_DQ27
DQ27
56
M_A_DQ28
DQ28
58 M_A_DQ29
DQ29
68 M_A_DQ30
DQ30
70
M_A_DQ31
10,4,8,9
DQ31
129 M_A_DQ32
DQ32
131
M_A_DQ33
DQ33
141 M_A_DQ34
DQ34
143 M_A_DQ35
DQ35
130
M_A_DQ36
DQ36
132 M_A_DQ37
DQ37
140
M_A_DQ38
DQ38
142 M_A_DQ39
DQ39
147 M_A_DQ40
DQ40
149 M_A_DQ41
DQ41
157 M_A_DQ42
CHA_DIMM0=00
DQ42
159
M_A_DQ43
DQ43 CHA_DIMM1=01
146 M_A_DQ44
DQ44
148 M_A_DQ45
DQ45
158 M_A_DQ46
DQ46 3.3VS
160 M_A_DQ47
DQ47
163
M_A_DQ48
DQ48
165 M_A_DQ49
DQ49
175
M_A_DQ50 RN3 RN3
DQ50
177 M_A_DQ51 10K_8P4R_04 10K_8P4R_04
DQ51
164 M_A_DQ52 1 8
DQ52
166 M_A_DQ53 2 7
DQ53
174 M_A_DQ54 3 6 CHA_SA0_DIM0
DQ54
176 4 5
M_A_DQ55 CHA_SA1_DIM0
DQ55
181 M_A_DQ56
DQ56
183 M_A_DQ57
DQ57
191 M_A_DQ58
DQ58
193 M_A_DQ59
DQ59
180
M_A_DQ60
DQ60
182 M_A_DQ61
DQ61 192
M_A_DQ62
DQ62
194 M_A_DQ63
DQ63
C616 C616 C603 C603 C613 C613 C615 C615 C604 C604 C614 C614
10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
C618 C618 C621 C621 C612 C612 C605 C605
0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04 0.1u_10V_X7R_04
10,11,12,13,14,15,16,17,18,19,2,20,21,22,23,24,25,26,27,28,3,31,32,33,34,35,36,37,38,39,43,46,8,9
3
2 1
JDIMM1B JDIMM1B
VDDQ
75 44
VDD1 VSS16
76 48
VDD2 VSS17
81 49
VDD3 VSS18
82 54
VDD4 VSS19
87 55
VDD5 VSS20
88 60
VDD6 VSS21
93 61
VDD7 VSS22
94 65
VDD8 VSS23
99 66
3.3VS
VDD9 VSS24
100 71
20mils
VDD10 VSS25
105 72
VDD11 VSS26
106 127
VDD12 VSS27
C157 C157 C153 C153 111 128
VDD13 VSS28
112 133
VDD14 VSS29
1u_6.3V_X5R_04 1u_6.3V_X5R_04 0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 117 134
VDD15 VSS30
118 138
VDD16 VSS31
123 139
VDD17 VSS32
124 144
VDD18 VSS33
145
VSS34
199 150
VDDSPD VSS35
151
VSS36
77 155
NC1 VSS37
122 156
NC2 VSS38
R228 R228 *10K_04 *10K_04 125 161
NCTEST VSS39
162
VSS40
198 167
10,8,9 TS#_DIMM0_1 EVENT# VSS41
30 168
DDR3_DRAMRST#
RESET# VSS42
172
VSS43
173
VSS44
MVREF_DQ_DIMMA 1 178
VREF_DQ VSS45
126 179
8 SM_VREF_A VREF_CA VSS46
184
VSS47
185
VSS48
2 189
VSS1 VSS49
3 190
VSS2 VSS50
8 195
VSS3 VSS51
9 196
VSS4 VSS52
13
VSS5
14
VSS6
19
VSS7
VTT_MEM
20
VSS8
25
VSS9
26 203
VSS10 VTT1
31 204
VSS11 VTT2
32
VSS12
37 GND1
VSS13 G1
38 GND2
VSS14 G2
43
CHA_SA0_DIM1 8 VSS15
CHA_SA1_DIM1 8
DS2SK-20401 -TR4B DS2SK-20401 -TR4B
VDDQ
R703 R703
DIMM
1K_1%_04 1K_1%_04
R691 R691
1.8_1%_04 1.8_1%_04
4 SA_DIMM_VREFDQ MVREF_DQ_DIMMA
C659 C659 C642 C642
C620 C620 R704 R704
0.022u_16V_X7R_04 0.022u_16V_X7R_04 1K_1%_04 1K_1%_04
1u_6.3V_X5R_04 1u_6.3V_X5R_04
R661 R661
24.9_1%_04 24.9_1%_04
Title Title Title
[07] DDR3 CHA SO-DIMM_0 [07] DDR3 CHA SO-DIMM_0 [07] DDR3 CHA SO-DIMM_0
3.3VS
Size Size Size Document Number Document Number Document Number
6-71-P7500-D03A 6-71-P7500-D03A 6-71-P7500-D03A
10,3,41,5,8,9 VDDQ
A3 A3 A3 SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
10,41,8,9 VTT_MEM
Date: Date: Date: Wednesday, October 29, 2014 Wednesday, October 29, 2014 Wednesday, October 29, 2014 Sheet Sheet Sheet 7 7 7
2 1
D
C
B
8
A
Rev Rev Rev
3.0 3.0 3.0
of of of 58 58 58