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Schematic Diagrams
Processor 2/5
D
46
Sheet 3 of 57
Processor 2/5
C
B
CFG STRAPS FOR PROCESSOR
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
PCIE PORT BIFURCATION STRAPS
A
CFG[4]: Reserved configuration lane. A test point may be
placed on the board for this lane.
CFG[19:7]: Reserved configuration lanes. A test point may
be placed on the board for these lands.
Configuration Signals: The CFG signals have a default value of
'1' if not terminated on the board.
B - 4 Processor 2/5
5
4
Haswell Processor 2/7 ( MISC,JTAG,CLK )
21
CLK_EXP_N
21
CLK_EXP_P
46
H_CPU_SVIDCLK
46
H_CPU_SVIDDAT
H_CPU_SVIDALRT#
R39
R39
44.2_1%_04
44.2_1%_04
H_CPU_SVIDALRT#
PMSYS_PWRGD_BUF
R568
R568
0_04
0_04
H_CPUPWRGD
17
H_CPUPWRGD
PCH_PLTRST_CPU
R503
R503
0_04
0_04
16
PCH_PLTRST_CPU
16
H_PM_SYNC
16,31
H_PECI
R482
R482
0_04
0_04
H_PROCHOT#
46
H_PROCHOT#
R468
R468
*10mil_short
*10mil_short
16
H_THRMTRIP#
R469
R469
1K_04
1K_04
1.05VS
17
H_SKTOCC#
8
SM_VREF
VCCIO_OUT
SVID Signals
R511
R511
R508
R508
R35
R35
75_04
75_04
H_CPU_SVIDALRT#
R45
R45
*90.9_1%_04
*90.9_1%_04
H_CPU_SVIDCLK
R500
R500
R38
R38
110_1%_04
110_1%_04
H_CPU_SVIDDAT
R498
R498
R44
R44
*100_04
*100_04
H_CPU_SVIDALRT#_R
R516
R516
2
CFG13
Processor Pullups/Pull downs
VCCIO_OUT
R484
R484
51_04
51_04
H_PROCHOT#
R515
R515
10K_04
10K_04
H_CPUPWRGD
C544
C544
*0.1u_16V_Y5V_04
*0.1u_16V_Y5V_04
TRACE WIDTH 10MIL, LENGTH <500MILS
R473
R473
H_PROCHOT#
Q35
Q35
MTN7002ZHS3
MTN7002ZHS3
C508
C508
G
31
H_PROCHOT_EC
47P_50V_NPO_04
47P_50V_NPO_04
R485
R485
100K_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
5
4
3
U42E
U42E
?
?
HASWELL
HASWELL
V4
G39
XDP_BPM0
BCLK#
BPM#[0]
V5
J39
XDP_BPM1
REV = 1.1
REV = 1.1
BCLK
BPM#[1]
G38
XDP_BPM2
BPM#[2]
C38
H37
H_CPU_SVIDCLK
XDP_BPM3
VIDSCLK
BPM#[3]
H_CPU_SVIDDAT
C37
H38
XDP_BPM4
VIDSOUT
BPM#[4]
H_CPU_SVIDALRT#_R
B37
J38
XDP_BPM5
VIDALERT
BPM#[5]
K39
XDP_BPM6
BPM#[6]
PMSYS_PWRGD_BUF_R
AK21
K37
XDP_BPM7
SM_DRAMPWROK
BPM#[7]
AB35
T35
PWRGOOD
RSVD_T35
CPU_RST#
M39
M38
RESET
RSVD_M38
P36
P6
TESTLO_P6
PM_SYNC
TESTLO_P6
N37
K9
VCCST
PECI
FC_K9
H15
RSVD_H15
H_CATERR#
M36
J9
CATERR
RSVD_J9
K38
H14
H_PROCHOT#_R
PROCHOT
RSVD_H14
H_THRMTRIP#_R
F37
M8
VCORE
THERMTRIP
VCC_M8
D38
AV2
SKTOCC
RSVD_AV2
J16
RSVD_TP_J16
AB38
H16
SM_VREF
RSVD_TP_H16
N40
PWR_DEBUG#
PWR_DEBUG
CFG0
AA37
N39
CFG[0]
VSS_N39
Y38
V7
CFG1
CFG[1]
VSS_V7
*1K_04
*1K_04
CFG2
AA36
AB6
CFG[2]
VSS_AB6
*1K_04
*1K_04
W38
K13
CFG3
CFG[3]
RSVD_TP_K13
CFG4
V39
J8
CFG[4]
RSVD_TP_J8
*1K_04
*1K_04
CFG5
U39
R1
SM_RCOMP_0
CFG[5]
SM_RCOMP[0]
*1K_04
*1K_04
CFG6
U40
P1
SM_RCOMP_1
CFG[6]
SM_RCOMP[1]
CFG7
V38
R2
SM_RCOMP_2
CFG[7]
SM_RCOMP[2]
CFG8
T40
AB36
CFG[8]
RSVD_AB36
CFG9
Y35
AW2
CFG[9]
RSVD_TP_AW2
*1K_04
*1K_04
AA34
AV1
CFG10
CFG[10]
RSVD_TP_AV1
CFG11
V37
AC8
CFG[11]
RSVD_AC8
Y34
P4
CFG12
VCCIOA_OUT
CFG[12]
VCOMP_OUT
CFG13
U38
U8
CFG[13]
RSVD_U8
CFG14
W34
AB33
CFG[14]
RSVD_AB33
V35
T8
CFG15
CFG[15]
VSS_T8
Y8
RSVD_Y8
Y36
M10
CFG17
CFG[17]
RSVD_M10
CFG16
Y37
L10
CFG[16]
RSVD_L10
V36
M11
CFG19
CFG[19]
RSVD_M11
CFG18
W36
L12
CFG[18]
RSVD_L12
W8
RSVD_W8
XDP_TCLK
D39
R33
TCK
RSVD_R33
XDP_TDI_R
F38
P33
TDI
RSVD_P33
F39
E40
XDP_TDO_R
VCC_SENSE_R
TDO
VCC_SENSE
XDP_TMS
E39
TMS
N33
VSS_N33
XDP_TRST#
E37
J11
TRST
VSS_J11
L39
M9
XDP_PRDY#
PRDY
VSS_M9
XDP_PREQ#
L37
J7
PREQ
VSS_J7
XDP_DBR_R
G40
F40
VSS_SENSE_R
DBR
VSS_SENSE
49.9_1%_04
49.9_1%_04
TESTLO_N5
N5
N35
TESTLO_N5
RSVD_N35
K8
W6
DPLL_REF_CLKN
RSVD_TP_K8
DPLL_REF_CLK#
J10
W5
DPLL_REF_CLKP
RSVD_TP_J10
DPLL_REF_CLK
H40
CFG_RCOMP
CFG_RCOMP
5 OF 10
5 OF 10
CFG_RCOMP 12MIL
3H993821-4M41-02H
3H993821-4M41-02H
?
?
CPU SOCKET -- LGA1150
S3 circuit:- DRAM PWR GOOD
logic
3.3V
3.3V
C556
C556
VDDQ
R555
R555
R556
R556
R571
R571
1.82K_1%_04
1.82K_1%_04
1
17
PM_DRAM_PWRGD
4
PMSYS_PWRGD_BUF
2
R569
R569
U44
U44
*MC74VHC1G08DFT1G
*MC74VHC1G08DFT1G
R566
R566
0_04
0_04
G
12,14,15,41,42,43,44
SUSB
10,11,12,13,14,15,16,17,18,19,2,20,21,22,23,24,25,26,27,28,31,32,33,34,35,36,37,38,39,43,46,7,8,9
11,17,2,22,24,25,26,27,30,36,37,39,40,41,43,44
3
2
1
PU/PD for JTAG signals
VCCIO_OUT
XDP_TMS
R31
R31
*51_04
*51_04
XDP_TDI_R
R472
R472
*51_04
*51_04
XDP_TDO_R
R40
R40
51_04
51_04
XDP_TCLK
R36
R36
51_04
51_04
R479
R479
49.9_1%_04
49.9_1%_04
XDP_TRST#
R470
R470
51_04
51_04
XDP_TDO_R
R41
R41
*100_04
*100_04
XDP_DBR_R
R471
R471
1K_04
1K_04
PWR_DEBUG#
R502
R502
150_1%_04
150_1%_04
R501
R501
*10K_04
*10K_04
DDR3 Compensation Signals
SM_RCOMP_0
R474
R474
100_1%_04
100_1%_04
SM_RCOMP_1
R476
R476
75_1%_04
75_1%_04
R475
R475
100_1%_04
100_1%_04
SM_RCOMP_2
VCORE
Close to CPU side
R33
R33
10_04
10_04
VCC_SENSE_R
R42
R42
0_04
0_04
VCORE_VCC_SENSE
VSS_SENSE_R
R43
R43
0_04
0_04
VCORE_VSS_SENSE
R34
R34
10_04
10_04
R490
R490
*0_04
*0_04
CLK_DPNS_N
21
R486
R486
*0_04
*0_04
CLK_DPNS_P
21
R467
R467
49.9_1%_04
49.9_1%_04
Supports external Graphics
No integrated graphic and eDP
DPLL_REF_CLKN
R491
R491
1K_04
1K_04
DPLL_REF_CLKP
R487
R487
1K_04
1K_04
Buffered reset to CPU
R495
R495
*2K_1%_04
*2K_1%_04
CPU_RST#
15,18,39
PLT_RST#
R494
R494
*1K_1%_04
*1K_1%_04
R567
R567
R572
R572
*39_04
*39_04
*100K_04
*100K_04
Q40
Q40
*MTN7002ZHS3
*MTN7002ZHS3
6
VCCST
2,5
VCCIOA_OUT
46,47,5,6
VCORE
Title
Title
Title
3.3VS
[03] Processor 2/5-CLK,MISC
[03] Processor 2/5-CLK,MISC
[03] Processor 2/5-CLK,MISC
3.3V
10,41,5,7,8,9
VDDQ
Size
Size
Size
Document Number
Document Number
Document Number
20,24,40,46,6
1.05VS
6-71-P7500-D03A
6-71-P7500-D03A
6-71-P7500-D03A
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
46,5,6
VCCIO_OUT
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Sheet
Sheet
Sheet
3
3
3
of
of
of
2
1
1.05VS
D
3.3VS
1.05VS
C
46
46
1.05VS
B
A
Rev
Rev
Rev
3.0
3.0
3.0
58
58
58
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