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ASM1182e PCIE 1 to 2
5
3.3VS
PR103
PR103
*10K_04
*10K_04
3.3VS
1A
PU8
PU8
3
VIN
VCNTL
1
PC91
PC91
PC92
PC92
1.2V PG
POK
10u_6.3V_X5R_06
10u_6.3V_X5R_06
0.1u_10V_X5R_04
0.1u_10V_X5R_04
D
2
3.3VS
EN
8
GND
9
3.3VS
GND
R389
R389
APE8981MP-B
APE8981MP-B
100K_04
100K_04
R388
R388
*100K_04
*100K_04
D
D
PC95
PC95
Q20A
Q20A
2
*MTDN7002ZHS6R
*MTDN7002ZHS6R
*0.1u_10V_X5R_04
*0.1u_10V_X5R_04
G
G
S
S
D
D
Q20B
Q20B
BUF_PLT_RST#
5
*MTDN7002ZHS6R
*MTDN7002ZHS6R
G
G
S
S
C
1
VSUS33_82
2
ASM1182_RST#
26,37
ASM1182_RST#
BUF_PLT_RST#
3
18,24,26,31,32,38
BUF_PLT_RST#
4
GPIO0_82
GPIO2_82
5
R836
R836
0_04
0_04
MSCL_82
6
10,17,27,28,7,8,9
SMB_CLK
7
R837
R837
0_04
0_04
MSDA_82
10,17,27,28,7,8,9
SMB_DATA
GPIO4_82
8
TEST_EN_82
9
10
VDDA33_82
11
VDD12_82
12
12.1K_1%_04
12.1K_1%_04
R362
R362
REXT1_82
Thermal via hole pattern
VCC12_82
VDDA33_82
B
pin 49
R325
R325
0_06
0_06
3.3V
VSUS33_82
R360
R360
0_06
0_06
VCC12_82
VDD12_82
C392
C392
10u_6.3V_X5R_06
10u_6.3V_X5R_06
C393
C393
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
C390
C390
10u_6.3V_X5R_06
10u_6.3V_X5R_06
VCC12_82
C391
C391
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
C383
C383
10u_6.3V_X5R_06
10u_6.3V_X5R_06
VCC33_82
C382
C382
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
A
C373
C373
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 14
VCC33_82
5
4
3
5VS
PC90
PC90
SHORT
1u_10V_Y5V_06
1u_10V_Y5V_06
4
PJ17
PJ17
VCC12_82
1.2VS
1A
6
1
2
VOUT
5
3mm
3mm
NC
PR104
PR104
PC96
PC96
PC94
PC94
PC93
PC93
Ra
7
4.99K_1%_04
4.99K_1%_04
82p_50V_NPO_04
82p_50V_NPO_04
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
VFB
PR105
PR105
Rb
10K_1%_04
10K_1%_04
Vout = 0.8V ( 1 + Ra / Rb )
VCC12_82
VDDA33_82
TXN_0_82
C327
C327
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCIE_RXN4_ASM1182
TXP_0_82
C328
C328
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCIE_RXP4_ASM1182
PCIE_TXN4_ASM1182
PCIE_TXP4_ASM1182
VDD12_82
R324
R324
12.1K_1%_04
12.1K_1%_04
REXT2_82
U35
U35
36
VCC12_82
VSUS33
VCC12_2
35
PE_RST_OUT#
PECLKN_0
34
PE_RST#
PECLKP_0
33
CLK_PCIE_MINI#
GPIO0
PECLKN_7
32
CLK_PCIE_MINI
GPIO2
PECLKP_7
31
VDD12_82
MSCL
VDD12_2
30
PCIE_RXN4_WLAN
MSDA
RXN_7
29
GPIO4
RXP_7
PCIE_RXP4_WLAN
28
TXN_7_82
C343
C343
0.1u_10V_X7R_04
0.1u_10V_X7R_04
TEST_EN
TXN_7
PCIE_TXN4_WLAN
27
C351
C351
0.1u_10V_X7R_04
0.1u_10V_X7R_04
7x7 mm
7x7 mm
TXP_7_82
PCIE_TXP4_WLAN
VDDA33_0
TXP_7
26
VDDA33_82
VDD12_0
VDDA33_2
25
REXT1
GPIO3
GPIO3_82
PPA1.0
PPA1.0
ASM1182e
ASM1182e
VCC33_82
GPIO1_82
CLK_PCIE_GLAN#
37
CLK_PCIE_GLAN
37
VDD12_82
PCIE_RXN3_GLAN
37
PCIE_RXP3_GLAN
37
TXN_5_82
C377
C377
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCIE_TXN3_GLAN
37
TXP_5_82
C376
C376
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCIE_TXP3_GLAN
37
R364
R364
0_06
0_06
3.3VS
VCC33_82
R355
R355
0_06
0_06
VCC33_82
VDDA33_82
VDD12_82
C364
C364
10u_6.3V_X5R_06
10u_6.3V_X5R_06
C363
C363
2.2u_6.3V_X5R_06
2.2u_6.3V_X5R_06
C353
C353
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 10
VDDA33_82
VCC12_82
C375
C375
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 14
C345
C345
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 26
C330
C330
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 44
11,12,13,14,15,27,28,29,30,31,33,35,36,43,44
11,17,2,22,24,25,26,27,3,30,37,39,40,41,43,44
11,12,13,14,15,27,28,29,30,31,33,35,36,43,44
10,11,12,13,14,15,16,17,18,19,2,20,21,22,23,24,25,26,27,28,3,31,32,33,34,35,37,38,39,43,46,7,8,9
4
3
2
HW STRAP
Pins
Function
GPIO0 Clock buffer mode setting. 0: PLL mode; 1: bypass mode
GPIO1 Clock buffer termination enable. 0: disable; 1: enable
GPIO2 Reserved for test mode.
GPIO3 Reserved for ASM1187e
GPIO4 SMBus enable. Please refer to below SMBus/I2C table
GPIO5 SMBus address[0].
GPIO6 SMBus address[1].
GPIO7 SMBus address[2].
MSCL
I2C enable. Please refer to below SMBus/I2C table.
R327
R327
0 for PLL mode clock buffer
GPIO0_82
R357
R357
GPIO1_82
GPIO2_82
R330
R330
R353
R353
GPIO3_82
R334
R334
I2C EEROM enable
GPIO4_82
19
R323
R323
GPIO5_82
19
19
19
R322
R322
GPIO6_82
R321
R321
GPIO7_82
R332
R332
MSCL_82
R345
R345
TEST_EN_82
CLK_PCIE_ASM1182#
21
CLK_PCIE_ASM1182
21
26
26
26
26
26
26
C352
C352
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 11
C371
C371
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 19
C340
C340
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 31
C331
C331
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 38
C374
C374
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 13
C372
C372
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 22
C335
C335
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 36
C329
C329
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
Pin 45
Title
Title
Title
[36]ASM1182e PCIE 1 TO 2
[36]ASM1182e PCIE 1 TO 2
[36]ASM1182e PCIE 1 TO 2
5VS
3.3V
5VS
Size
Size
Size
Document Number
Document Number
Document Number
3.3VS
6-71-P7500-D03A
6-71-P7500-D03A
6-71-P7500-D03A
A3
A3
A3
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
2
Schematic Diagrams
1
Default (internal pull)
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
Pull up
D
Pull up
*1K_04
*1K_04
*1K_04
*1K_04
*1K_04
*1K_04
*1K_04
*1K_04
Sheet 36 of 57
*1K_04
*1K_04
*1K_04
*1K_04
ASM1182e PCIE 1
*1K_04
*1K_04
to 2
*1K_04
*1K_04
C
*1K_04
*1K_04
1K_04
1K_04
B
A
Rev
Rev
Rev
3.0
3.0
3.0
Sheet
Sheet
Sheet
36
36
36
of
of
of
58
58
58
1
ASM1182e PCIE 1 to 2 B - 37
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