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Power-Up Sequencing
(1) RTC_CVDD can be combined with PLL and RAM 1.2-V supplies if desired to turn off RTC when device is off. Otherwise, power
RTC_CVDD separately with a dedicated power source.
(2) Sequencing 1.2-V supplies:
(a) RTC (RTC_CVDD) may be powered from an external device (such as a battery) before all other supplies are applied. If the
RTC is not used, RTC_CVDD must be connected to CVDD.
(b) Group 2a: CVDD core logic supply. CVDD can support 1.3 V, in this case SMPS (VDD1) supplying CVDD core can be set
to 1.3 V after initial power up.
(c) Group 2b: Other 1.2-V logic supplies (RVDD, PLL0_VDDA). Groups 2a and 2b may be powered up together or 2a first
followed by 2b.
NOTE: To correctly power on the device, the PWRHOLD signal must be high after PWRON is
pressed. In this configuration the PWRHOLD signal on TPS65910 is connected to VIO.
PWRHOLD transitions to high when VIO powers up.
3.3
Power-Up Sequence for TPS65910
To satisfy the power-up requirements for the OMAPL-138 and TMS320C6742/4/6 processorsprocessor,
the TPS65910 powers up with the default sequence when in the EEPROM boot mode configuration
(BOOT0 = 0 and BOOT1 = 1) (see
EEPROM (factory programmable only).
Apart from the main power rails required by the processors, all other rails are also powered up at initial
power up to support other system peripherals.
Figure 3
shows a typical power-up timing diagram.
Table 3
shows the power-up sequence.
TPS65910 Power Rail
(1)
PWRON
VDIG1
VDD1
VDD2
VIO
VDIG2
VAUX33
VMMC
VAUX1
VAUX2
VDAC
VPLL
(1)
The PWRON signal is the start-on event. All timings listed are with respect to the previous event.
8
TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x
Family of Processors
Table
3). The correct power-up sequence is configured in the
Table 3. Power-Up Sequence for TPS65910
Voltage (V)
–
1.2
1.2
1.2
1.8
1.2
3.3
3.3
1.8
3.3
1.8
1.8
Copyright © 2010–2015, Texas Instruments Incorporated
Sequence Number
–
1
2
3
4
4
5
5
6
6
7
7
SWCU071B – December 2010 – Revised October 2015
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www.ti.com
Delay (ms)
2
2
2
2
0
2
0
2
0
2
0
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