Epson S2R72A21 Application Note page 12

3.3.2.10 Disconnect Operation
When the Portable Device is detached during HS operation, the HS termination of the Portable Devices would be
vanished and the amplitude of the EXT port's HS signal would change from 400mV to 800mV. The validated HS
detector circuit (EXT port) would detect the amplitude variation by the SOF's EOP (with 40bit time length).
When the Portable Device is judged "Detach" then the S2R72A21 would transit to FS_LS state.
During this period, the USB signal path would switch from HS Synchronizer to Bus Switch and the INT port and
EXT port would be connected. Afterward the HS packet which is transmitted from the Host SoC would by pass
from INT port to EXT port via the Bus Switch. Since the HS termination of the detached Portable Device has
been vanished, the Host SoC output would have amplitude of 800mV. Due to this, the Host SoC would be able to
detect the Portable Device has been detached using the Host SoC's own HS disconnection detector circuit.
In case EN_DETACH=1, S2R72A21 would transit to DETACH state after detection of Portable Device. During
DETACH state, EXT port would be HiZ, since both the Bus Switch and the HS Synchronizer are stopped and the
internal USB path is disconnected. Due to this, the USB cable attached to the EXT port is omitted from the USB
signal path, so the Host SoC can detect the Portable Device detach with less influence of the returning wave.
When 3ms has passed, the S2R72A21 would transit to FS_LS state.
Figure 3.3.2.10.1 shows the disconnection operation waveform in case EN_DETACH=1.
HS
opearetion(1)
HVDD
XRESET
ENABLE
HS_Packet
INT_DP/DM
EXT_DP/DM
State
HS
USB signal
HS Synchronizer
path
Figure 3.3.2.10.1 Disconnection operation waveform in case EN_DETACH=1
3.3.2.11 Operation end
The Host SoC can notify the Detach detection to the S2R72A21 by ENABLE=0 once the Host SoC has detected
the Detach of the Portable Device. The S2R72A21 would transit to DISCONNECT state when ENABLE=0.
Here the connection of the INT port and the EXT port is maintained. Both the INT port and the EXT port would
be VSS level due to the pull down resistor of the Host SoC.
Afterward, the S2R72A21 would start operation by ENABLE=1 again, and then the S2R72A21 is ready to accept
re-attach of the Device.
Please note that the S2R72A21 would also transit to DISCONNECT state by setting XRESET 0→1 and 10ms
passes by. After detecting ENABLE=1, the S2R72A21 is ready to accept re-attach.
10
Suspend
operation
J
Suspend
3ms
J
Detect SE0
for 3ms
FS_LS
Bus Switch (INT-EXT)
Seiko Epson Corporation
Resume HS
operation opearation(2)
▼ Detach
Resume
SOF SOF
K
5us
K
Detect SE0
for 5us
HS
HS Synchronizer
Disconnect Operation
operation end
3ms
SOF SOF
SOF
Hi-Z
HS detach 3ms Detect
detection passed ENABLE=0
DETACH FS_LS DISCONNECT
Bus Switch
Bus Switch (INT-EXT)
(OFF)
S2R72A21 Application Note
(Rev.1.00)