Table of Contents
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User Guide
HARDWARE DESCRIPTION
JUMPERS AND CONNECTORS
Table 1. Connector and Jack Descriptions
Reference
Designator
Type
J1
DC jack
J2
Binding post
J5
2-pin header, 0.1 in. pitch
J6
6-pin header, 0.1 in. pitch
J7
2-pin header, 0.1 in. pitch
J8
3-pin header, 0.1 in pitch
J9
3-pin header, 0.1 in. pitch
J10
Binding post
J11
10-pin header, 0.1 in. pitch
J12
RCA cinch jack
J13
9-pin header, 0.1 in. pitch
J14
2-pin header, 0.1 in. pitch
J15
3-pin header, 0.1 in. pitch
J18
2-pin header, 0.1 in. pitch
J19
3-pin header, 0.1 in. pitch
J20
3-pin header, 0.1 in. pitch
J21
3-pin header, 0.1 in. pitch
J22
2-pin header, 0.1 in. pitch
J23
2-pin header, 0.1 in. pitch
J24
2-pin header, 0.1 in. pitch
J25
2-pin header, 0.1 in. pitch
J26
2-pin header, 0.1 in. pitch
J27
2-pin header, 0.1 in. pitch
J28
2-pin header, 0.1 in. pitch
J29
2-pin header, 0.1 in. pitch
J30
2-pin header, 0.1 in. pitch
J31
2-pin header, 0.1 in. pitch
J32
2-pin header, 0.1 in. pitch
J33
3-pin header, 0.1 in. pitch
J34
2-pin header, 0.1 in. pitch
J35
3-pin header, 0.1 in. pitch
J36
2-pin header, 0.1 in. pitch
J37
4-pin header, 0.1 in. pitch
J38
4-pin header, 0.1 in. pitch
J39
4-pin header, 0.1 in. pitch
J40
4-pin header, 0.1 in. pitch
JP1
3-pin header, 0.1 in. pitch
JP2
2-pin header, 0.1 in. pitch
JP3
2-pin header, 0.1 in. pitch
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Functional Name
Description
5 V dc input
Barrel jack that provides external power to the EVAL-SSM6515. J1 accepts a 3.8 V dc to 5 V
dc input.
5 V
Binding post used to connect the external 5 V supply to the EVAL-SSM6515.
PVDD (AMP1)
Jumper connects PVDD to the
IOVDD select
Used to select the IOVDD source: 1.2 V regulator, 1.8 V regulator, or external 1.8 V IOVDD
source.
External PVDD
Used to connect the external 1.8 V PVDD supply.
Pulse density modulation
Used to select the PDM left and right channels for AMP1 in standalone mode.
(PDM) LR_SEL (AMP1)
Mode select (AMP1)
Used to select the I
GND
Connect to GND or 0 V of the power supply.
USB interface (USBi) header 10-pin header used to connect the USBi.
Coaxial S/PDIF input
Used to connect the coaxial S/PDIF input.
2
S/PDIF, external I
S, PDM
9-pin header for selecting the internal input source (S/PDIF) or connecting the external
2
Input
I
S/PDM input source for the amplifiers.
S/PDIF master clock (MCLK)
Used to access the recovered master clock from the S/PDIF receiver.
out
2
I
S/PDM select (AMP1)
Used to select the left and right channel in I
MHz for AMP1 in PDM standalone mode.
PVDD (AMP2)
Jumper connects PVDD to the SSM6515 (AMP2).
PDM LR_SEL (AMP2)
Used to select the PDM left and right channels for AMP2 in standalone mode.
2
I
S/PDM select (AMP2)
Used to select the I
2
I
S/PDM select (AMP2)
Used to select the left and right channels in I
6 MHz for AMP2 in PDM standalone mode.
2
I
C SCL (AMP2)
Jumper connects the USBi SCL to AMP2. Leave open in standalone mode.
2
I
C SDA (AMP2)
Jumper connects the USBi SDA to AMP2. Leave open in standalone mode.
2
I
C SCL (AMP1)
Jumper connects the USBi SCL to AMP1. Leave open in standalone mode.
2
I
C SDA (AMP1)
Jumper connects the USBi SDA to AMP1. Leave open in standalone mode.
FSYNC
Jumper connects FSYNC to AMP2. Leave open for PDM in standalone mode.
FSYNC
Jumper connects FSYNC to AMP1. Leave open for PDM in standalone mode.
IOVDD (AMP1)
Jumper connects IOVDD to the SSM6515 (AMP1).
IOVDD (AMP2)
Jumper connects IOVDD to the SSM6515 (AMP2).
Do not use
Leave this jumper open (Reserved for internal use).
Do not use
Leave this jumper open (Reserved for internal use).
External IOVDD
Used to connect the external 1.2 V to 1.8 V IOVDD supply.
2
I
C address select (AMP2)
J33 and J34 are used to select the I
mode.
2
I
C address select (AMP2)
J33 and J34 are used to select the I
2
I
C address select (AMP1)
J35 and J36 are used to select the I
mode.
2
I
C address select (AMP1)
J35 and J36 are used to select the I
AMP1 output
AMP1 pre-filter output.
AMP1 output
AMP1 pre-filter output.
AMP2 output
AMP2 post-filter output.
AMP2 output
AMP2 post-filter output.
PVDD select
Used to select the 1.8 V regulator or external 1.8 V PVDD source.
S/PDIF reset jumper
Shunt JP2 to keep the S/PDIF receiver in reset.
SD_OSC (active low)
Shunt JP3 to disable the 12.288 MHz oscillator input to the S/PDIF receiver.
EVAL-SSM6515
SSM6515
(AMP1).
2
S or PDM mode for AMP1 in standalone mode.
2
S standalone mode or the PDM_FS of 3 MHz or 6
2
S or PDM input for AMP2 in standalone mode.
2
S standalone mode or the PDM_FS of 3 MHz or
2
C address for AMP2. Connect J33 to PVDD in standalone
2
C address for AMP2. Shunt J34 in standalone mode.
2
C address for AMP1. Connect J35 to PVDD in standalone
2
C address for AMP1. Shunt J36 in standalone mode.
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