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SiT6722EBB Evaluation Board User Manual
Contents
1 Introduction ............................................................................................................................................. 1
2 I/O Descriptions ....................................................................................................................................... 2
3 EVB Usage Descriptions ........................................................................................................................... 3
3.1 EVB Configurations........................................................................................................................ 3
2
3.1.1 I
C Support ....................................................................................................................... 3
3.2 Waveform Capturing Using Active Probe ..................................................................................... 4
3.3 Measuring Jitter and Phase Noise ................................................................................................. 5
3.4 Current Measurement .................................................................................................................. 6
Appendix A .................................................................................................................................................... 7
1
Introduction
The SiT6722EBB evaluation board (EVB) is designed for use with SiTime's Elite Super-TCXOs in the
10-pin, 5.0 x 3.2 mm x mm ceramic packages and LVCMOS output type. It enables the evaluation of key
functionalities of these precision Super-TCXOs in three configuration modes: TCXO, VCTCXO and
2
DCTCXO with I
C.
The SiT6722EBB supports 5.0 x 3.2 mm x mm package size including the following products:
Base Part Number
SiT5155
SiT5156
SiT5157
SiT5356
SiT5357
SiT5358
SiT5359
SiT5186
SiT5187
SiT5386
SiT5387
SiT5146
SiT5147
SiT5346
SiT5347
SiT5348
SiT5349
SiT6722EBB User Manual | Rev 1.2
Type
Super-TCXO
Super-TCXO
Super-TCXO
Super-TCXO
Super-TCXO
Super-TCXO
Super-TCXO
Automotive Super-TCXO
Automotive Super-TCXO
Automotive Super-TCXO
Automotive Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Page 1 of 10
Output frequency
10 MHz - 40 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
1 MHz - 60 MHz
60.000001 MHz - 220 MHz
Package
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
5.0 x 3.2 CQFN
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Summary of Contents for SiTime SiT6722EBB
-
Page 1: Table Of Contents
Appendix A ..............................7 Introduction The SiT6722EBB evaluation board (EVB) is designed for use with SiTime’s Elite Super-TCXOs in the 10-pin, 5.0 x 3.2 mm x mm ceramic packages and LVCMOS output type. It enables the evaluation of key functionalities of these precision Super-TCXOs in three configuration modes: TCXO, VCTCXO and DCTCXO with I The SiT6722EBB supports 5.0 x 3.2 mm x mm package size including the following products:... -
Page 2: O Descriptions
Probing points for accurate waveform measurement Connector access for controlling the output frequency via I SiTime typically ships the EVB with the Super-TCXO mounted using SiTime recommended reflow profile. The Super-TCXO device should only be evaluated in its original soldered down state for best signal integrity and frequency stability. -
Page 3: Evb Usage Descriptions
“DNP” are not assembled. Shipment Configuration SiT6722EBB is shipped configured for buffered output allowing connecting it to the instrument input using 50 Ω coax cable. Details on the board assembly for shipment configuration can be found on the schematic (see... -
Page 4: Waveform Capturing Using Active Probe
For waveform measurement, it's recommended to remove resistor R17. Please refer to Figure A2 test point locations on the SiT6722EBB. If the soldering probe is used, it is recommended to use R21 resistor pads or solder it over it if necessary... -
Page 5: Measuring Jitter And Phase Noise
Figure 2: Signal measurement using probe Measuring Jitter and Phase Noise For jitter and phase noise measurements, buffered output configuration is recommended. SiTime TCXO was not designed to drive 50 Ω load directly so buffer avoids excessive current draw from the device output. -
Page 6: Current Measurement
It is recommended to measure the voltage on DUT VDD and adjust for any drop on the DMM to ensure known VDD voltage on the device. VDD adjustment must be completed before every current measurement. SiT6722EBB User Manual | Rev 1.2 Page 6 of 10 www.sitime.com... - Page 7 Buff_VCC Buff_Out 0.1uF LMK1C1102PWR Buff_Out VDD_filt Pad4 Pad3 Output Pin1 Pad5 LVCMOS-to-sine wave filter option Pad6 Pad7 Pad8 Pad9 Pad10 Pad11 Pad12 Pad13 Pad14 Figure A1: SiT6722EBB electrical schematics SiT6722EBB User Manual | Rev 1.2 Page 7 of 10 www.sitime.com...
- Page 8 Connectors part number mating connector associated products Power/Power adjust WM10299-ND WM2002-ND WM1114TR-ND Buffer power WM10297-ND WM2011-ND Buffer power supply jumper Z5275-ND S9342-ND Frequency control via I 2057-PH1RB-04-UA-ND SiT6722EBB User Manual | Rev 1.2 Page 8 of 10 www.sitime.com...
- Page 9 SiT6722EBB Evaluation Board User Manual Probe test points VDD sense Signal Figure A2: SiT6722EBB layout SiT6722EBB User Manual | Rev 1.2 Page 9 of 10 www.sitime.com...
- Page 10 © SiTime Corporation, December 2024. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
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