Motorola M68HC08 Reference Manual page 34

BLDC Motor Control
NOTE:
Designer Reference Manual
34
Freescale Semiconductor, Inc.
I
d0
+
u /2 S
=
d At
-
+
u /2
=
S
d
Ab
-
Figure 3-9. Mutual Capacitance Model
Let us focus on the situation when the motor phase A is switched from
negative dc-bus rail to positive, and the phase B is switched from
positive to negative. This is described by these conditions
u =
VA
The voltage that disturbs the back-EMF sensing, utilizing the free (not
powered) motor phase C, can be calculated based the equation:
1
u = -- - u +
VC Cap Ccb
2
The final expression for disturbing voltage can be found as follows:
1

u = -- - ------- -

VC Cap
2 C
(EQ 3-10.) expresses the fact that only the unbalance of the mutual
capacitance (not the capacitance itself) disturbs the back-EMF sensing.
When both capacities are equal (they are balanced), the disturbances
disappear. This is demonstrated in
BLDC Motor Control
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S
Bt
u
VA
u
Cba
I
S
Sb
Bb
u
S S PWM
Ab Bt
1 1 1
– -- - u -- - u u = -- - u
d d VB d
2 2 2
i = i = i
Cac Ccb C
u + 2R – u + R
Cac C Ccb C
C –
1 1 1
 i 
∫
cb
– ------- - t d = -- - ----------------------
 
C
C 2 C
ac cb cb
Figure 3-10
A u
Cac
i
C
C
R
C
R
C
C
i
Cab
i
C
C
C
u
R
C Ccb
B
VB
(EQ 3-8.):
1
(EQ 3-8.)
– -- - u
d
2
1
= -- - u – u
(EQ 3-9.)
Cac Ccb
2
C
 i
∫
ac
t d (EQ 3-10.)

C
C
ac
and Figure 3-11.
DRM028 — Rev 0
MOTOROLA
u
VC Cap