Motorola M68HC08 Reference Manual page 104

Software Design
5.6.2 BLDC Commutation and Zero Crossing Selection
5.6.2.1 Preset BLDC Commutation and BEMF Zero Crossing Selection
5.6.2.2 Set BLDC Commutation and BEMF Zero Crossing Selection
Designer Reference Manual
104
Freescale Semiconductor, Inc.
The required BLDC motor voltage system commutation is provided
using the MC68HC08MR32 PWM block.
The zero crossing selection is provided by setting port F pins
PTF1–PTF3 connected to the multiplexer.
As shown in Data Flow, the commutation and back-EMF zero-crossing
selection process is split into two actions:
1. Preset BLDC commutation and BEMF zero-crossing selection
2. Set BLDC commutation and BEMF zero-crossing selection
In each phase of the 6-step commutation two PWM channels (bottom
and top switch) are active and the other four PWM channels are logical
0. The commutation preset is accomplished by setting the buffered
registers PVAL1H, PVAL1L through PVAL6H, PVAL6L. To preset the
active PWM channel, the MSB bits of the dedicated PVALxH registers
are set to 0.To preset the PWM channel to the logical 0, the MSB bits of
the dedicated PVALxH registers are set to 1. This is due to the signature
bit functionality as described in 68HC908MR32, 68HC9908MR16
Advance Information (Motorola document order number
MC68HC908MR32/D) .This commutation preset is provided by the
function Commut (). In Commut(), the function field
Set_PWM(P_Step_Cmt] () calls one of Shft_PWM0..5() functions
according to P_Step_Cmt value, so the PVALxH registers are set as
required. This will not effect the PWM signals until LDOK bit is set. Also,
the back-EMF zero crossing selection preset is provided in this function,
by setting V_MUX variable according to P_Step_Cmt value.
The commutation set is provided in timer 2 interrupt function
TIMACh3_Int() in the code_isr.c file. The PWMEN is toggled and
LDOK bit set, in order to immediately restart the PWM generator and
reload the PWM with the buffered PVAL1H, PVAL1L through PVAL6H,
Software Design
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