Output Signals; Default Operation And Jumper Selection Settings - Analog Devices AD911 Series User Manual

UG-073

OUTPUT SIGNALS

The evaluation board provides the option to evaluate the analog
outputs directly from the DAC (default) or the output of the RF
quadrature modulator ADL5375, driven by the DAC. The DAC
output can also be evaluated as a single-ended buffered output
with an op amp for applications requiring low frequency
signals.
The evaluation board also provides access on a connector to the
auxiliary DAC outputs. Finally, the evaluation board provides a
data clock output intended to synchronize the DPG2 evaluation
board with the AD911x or AD971x internal clock.
DEFAULT OPERATION AND
JUMPER SELECTION SETTINGS
This section explains the default and optional settings or modes
allowed on the AD911x and AD971x Rev. A evaluation boards.
Power Circuitry
Connect the USB cable to the USB Mini-B P1 connector.
The USB connections provide the power supply to the evalu-
ation board.
By default, the evaluation board provides on-board regulators to
supply the AD911x or AD971x (DVDD, CVDD, and AVDD)
as well as auxiliary circuits, such as the level translator (DVDDX)
and the clock distribution chip (CVDDX). These regulators can be
set up to regulate the primary voltage to 3.3 V or 1.8 V, depending
on the setting of the 2-position jumpers: JP22, JP26, JP29, JP88,
and JP89 (see Figure 2). Alternatively, external power supplies can
supply all the on-board components. The choice between internally
or externally regulated power supplies can be done individually per
power supply by two-position jumpers: JP6, JP10, JP54, JP15, and
JP78 (see Figure 2). These regulated voltages are then connected to
on-board filters to be used by the components on board.
Note that, for simplicity, it is recommended to use the USB-
powered option combined with the on-board regulation. The
choice of 3.3 V or 1.8 V regulation is left to the user depending
on application.
Table 1. Power Supply Jumpers
Jumper Position for
Voltage Regulation
Power
Supply
Output 3.3 V Default
CVDD JP22 1−2
DVDD JP26 1−2
AVDD JP29 1−2
DVDDX JP88 1−2
CVDDX JP89 1−2
1 1–2 means to place the jumper between Pin 1 and Pin 2; 2−3 means to place
the jumper between Pin 2 and Pin 3.
USB
ADP3334A
ADP3334A
ADP3334A
ADP3334A
ADP3334A
Figure 2. Power Supply Jumpers Schematic
Rev. 0 | Page 4 of 12
Evaluation Board User Guide
Jumper Position for
Internally or Externally
1
Level Regulated Voltage
1.8 V Internal Default
JP22 2−3 JP6 2−3
JP26 2−3 JP10 2−3
JP29 2−3 JP54 2−3
JP88 2−3 JP15 2−3
JP89 2−3 JP78 2−3
FILTER
CVDD_IN
2 1
1.8V
JP6
3
2
JP22
1
3.3V
FILTER
DVDD_IN
2 1
1.8V JP10
3
2
JP26
1
3.3V
FILTER
AVDD_IN
2 1
1.8V
JP54
3
2
JP29
1
3.3V
FILTER
DVDD _IN
X
2 1
1.8V JP15
3
2
JP88
1
3.3V
FILTER
CVDD _IN
X
2 1
1.8V
JP78
3
2
JP89
1
3.3V
1
External
JP6 1−2
JP10 1−2
JP54 1−2
JP15 1−2
JP78 1−2
CVDD
DVDD
AVDD
DVDD
CVDD