User Manuals: Abov A96A148 8-bit Microcontroller

Manuals and User Guides for Abov A96A148 8-bit Microcontroller. We have 2 Abov A96A148 8-bit Microcontroller manuals available for free PDF download: User Manual

Abov A96A148 User Manual (296 pages)

Brand: Abov | Category: Microcontrollers | Size: 4 MB

Table of Contents
2
Description
18
Device Overview
18
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts
18
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (Continued)
19
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (Continued)
20
A96G140/A96G148/A96A148 Block Diagram
21
Figure 1. A96G140/A96G148/A96A148 Block Diagram
21
Pinouts and Pin Description
22
Pinouts
22
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment
22
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment
23
Figure 4. A96G140/A96G148 32LQFP Pin Assignment
24
Figure 5. A96G140/A96G148 32SOP Pin Assignment
25
Figure 6. A96G140/A96G148 28SOP Pin Assignment
25
Figure 7. A96A148 28SOP Pin Assignment
26
Pin Description
27
Table 2. Normal Pin Description
27
Table 2. Normal Pin Description (Continue)
28
Table 2. Normal Pin Description (Continue)
29
Table 2. Normal Pin Description (Continue)
30
Table 2. Normal Pin Description (Continue)
31
Port Structures
32
Figure 8. General Purpose I/O Port
32
Figure 9. External Interrupt I/O Port
33
Memory Organization
34
Program Memory
34
Data Memory
35
Figure 10. Program Memory Map
35
Figure 11. Data Memory Map
36
External Data Memory
37
Figure 12. Lower 128Bytes of RAM
37
SFR Map
38
SFR Map Summary
38
Figure 13. XDATA Memory Area
38
Table 3. SFR Map Summary
38
Table 3. SFR Map Summary (Continued)
39
Table 4. XSFR Map Summary
39
SFR Map
40
Table 5. SFR Map
40
Table 5. SFR Map (Continued)
41
Table 5. SFR Map (Continued)
42
Table 5. SFR Map (Continued)
43
Table 6. XSFR Map
44
Compiler Compatible SFR
45
5 I/O Ports
47
Port Register
47
Data Register (Px)
47
Direction Register (Pxio)
47
Pull-Up Register Selection Register (Pxpu)
47
Open-Drain Selection Register (Pxod)
47
Bounce Enable Register (Pxdb)
47
Port Function Selection Register (Pxfsr)
47
Register Map
48
Table 7. Port Register Map
48
P0 Port
49
P0 Port Description
49
Register Description for P0
49
P1 Port
52
P1 Port Description
52
Register Description for P1
52
P2 Port
56
P2 Port Description
56
Register Description for P2
56
P3 Port
58
P3 Port Description
58
Register Description for P3
58
P4 Port
60
P4 Port Description
60
Register Description for P4
60
P5 Port
62
P5 Port Description
62
Register Description for P5
62
Interrupt Controller
64
External Interrupt
65
Figure 14. Interrupt Group Priority Level
65
Block Diagram
66
Figure 15. External Interrupt Description
66
Figure 16. Interrupt Controller Block Diagram
67
Interrupt Vector Table
68
Table 8. Interrupt Vector Address Table
68
Interrupt Sequence
69
Effective Timing after Controlling Interrupt Bit
70
Figure 17. Interrupt Sequence Flow
70
Multi-Interrupt
71
Figure 18. Effective Timing of Interrupt Enable Register
71
Figure 19. Effective Timing of Interrupt Flag Register
71
Interrupt Enable Accept Timing
72
Figure 20. Effective Timing of Multi-Interrupt
72
Interrupt Service Routine Address
73
Saving/Restore General Purpose Registers
73
Figure 21. Interrupt Response Timing Diagram
73
Figure 22. Correspondence between Vector Table Address and the Entry Address of ISR
73
Figure 23. Saving/Restore Process Diagram and Sample Source
73
Interrupt Timing
74
Interrupt Register Overview
74
Interrupt Enable Register (IE, IE1, IE2, and IE3)
74
Interrupt Priority Register (IP and IP1)
74
Figure 24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
74
External Interrupt Flag Register (EIFLAG0 and EIFLAG1)
75
External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1)
75
Register Map
75
Interrupt Register Description
75
Table 9. Interrupt Register Map
75
Clock Generator
82
Clock Generator Block Diagram
82
Register Map
83
Register Description
83
Figure 25. Clock Generator Block Diagram
83
Table 10. Clock Generator Register Map
83
Basic Interval Timer
86
BIT Block Diagram
86
BIT Register Map
86
Figure 26. Basic Interval Timer Block Diagram
86
Table 11. Basic Interval Timer Register Map
86
BIT Register Description
87
Watchdog Timer
88
WDT Interrupt Timing Waveform
88
Figure 27. Watch Dog Timer Interrupt Timing Waveform
88
WDT Block Diagram
89
Register Map
89
Register Description
89
Figure 28. Watch Dog Timer Block Diagram
89
Table 12. Watchdog Timer Register Map
89
10 Watch Timer
91
WT Block Diagram
91
Register Map
91
Figure 29. Watch Timer Block Diagram
91
Watch Timer Register Description
92
Table 13. Watch Timer Register Map
92
Timer 0/1/2/3/4/5
94
Timer 0
94
8-Bit Timer/Counter Mode
94
Table 14. Timer 0 Operating Mode
94
Figure 30. 8-Bit Timer/Counter Mode for Timer 0
95
Figure 31. 8-Bit Timer/Counter 0 Example
95
8-Bit PWM Mode
96
Figure 32. 8-Bit PWM Mode for Timer 0
96
Figure 33. PWM Output Waveforms in PWM Mode for Timer 0
97
8-Bit Capture Mode
98
Figure 34. 8-Bit Capture Mode for Timer 0
98
Figure 35. Input Capture Mode Operation for Timer 0
99
Figure 36. Express Timer Overflow in Capture Mode
99
Timer 0 Block Diagram
100
Register Map
100
Register Description
100
Figure 37. 8-Bit Timer 0 Block Diagram
100
Table 15. Timer 0 Register Map
100
Timer 1
102
16-Bit Timer/Counter Mode
102
Table 16. TIMER 1 Operating Modes
102
Figure 38. 16-Bit Timer/Counter Mode of Timer 1
103
Figure 39. 16-Bit Timer/Counter Mode Operation Example
103
16-Bit Capture Mode
104
Figure 40. 16-Bit Capture Mode of Timer 1
104
16-Bit PPG Mode
105
Figure 41. 16-Bit Capture Mode Operation Example
105
Figure 42. 16-Bit PPG Mode of Timer 1
106
Figure 43. 16-Bit PPG Mode Operation Example
107
16-Bit Timer 1 Block Diagram
108
Register Map
108
Register Description
108
Figure 44. 16-Bit Timer 1 Block Diagram
108
Table 17. TIMER 1 Register Map
108
Timer 2
111
16-Bit Timer/Counter Mode
112
Table 18. TIMER 2 Operating Modes
112
Figure 45. 16-Bit Timer/Counter Mode of Timer 2
113
Figure 46. 16-Bit Timer/Counter Mode Operation Example
113
16-Bit Capture Mode
114
Figure 47. 16-Bit Capture Mode of Timer 2
114
Figure 48. 16-Bit Capture Mode Operation Example
115
Figure 49. Express Timer Overflow in Capture Mode
115
16-Bit PPG Mode
116
Figure 50. 16-Bit PPG Mode of Timer 2
116
Figure 51. 16-Bit PPG Mode Operation Example
117
16-Bit Timer 2 Block Diagram
118
Register Map
118
Register Description
118
Figure 52. 16-Bit Timer 2 Block Diagram
118
Table 19. TIMER 2 Register Map
118
Timer 3
121
16-Bit Timer/Counter Mode
121
Table 20. TIMER 3 Operating Modes
121
Figure 53. 16-Bit Timer/Counter Mode of Timer 3
122
Figure 54. 16-Bit Timer/Counter Mode Operation Example
122
16-Bit Capture Mode
123
Figure 55. 16-Bit Capture Mode of Timer 3
123
Figure 56. 16-Bit Capture Mode Operation Example
124
Figure 57. Express Timer Overflow in Capture Mode
124
16-Bit PPG Mode
125
Figure 58. 16-Bit PPG Mode of Timer 3
125
Figure 59. 16-Bit PPG Mode Operation Example
126
16-Bit Timer 3 Block Diagram
127
Register Map
127
Register Description
127
Figure 60. 16-Bit Timer 3 Block Diagram
127
Table 21. TIMER 3 Register Map
127
Timer 4
130
16-Bit Timer/Counter Mode
131
Table 22. TIMER 4 Operating Modes
131
Figure 61. 16-Bit Timer/Counter Mode of Timer 4
132
Figure 62. 16-Bit Timer/Counter Mode Operation Example
132
16-Bit Capture Mode
133
Figure 63. 16-Bit Capture Mode of Timer 4
133
Figure 64. 16-Bit Capture Mode Operation Example
134
Figure 65. Express Timer Overflow in Capture Mode
134
16-Bit PPG Mode
135
Figure 66. 16-Bit PPG Mode of Timer 4
135
Figure 67. 16-Bit PPG Mode Operation Example
136
16-Bit Timer 4 Block Diagram
137
Register Map
137
Register Description
137
Figure 68. 16-Bit Timer 4 Block Diagram
137
Table 23. TIMER 4 Register Map
137
Timer 5
140
16-Bit Timer/Counter Mode
140
Table 24. TIMER 5 Operating Modes
140
Figure 69. 16-Bit Timer/Counter Mode of Timer 5
141
Figure 70. 16-Bit Timer/Counter Mode Operation Example
141
16-Bit Capture Mode
142
Figure 71. 16-Bit Capture Mode of Timer 5
142
Figure 72. 16-Bit Capture Mode Operation Example
143
Figure 73. Express Timer Overflow in Capture Mode
143
16-Bit PPG Mode
144
Figure 74. 16-Bit PPG Mode of Timer 5
144
Figure 75. 16-Bit PPG Mode Operation Example
145
16-Bit Timer 5 Block Diagram
146
Register Map
146
Register Description
146
Figure 76. 16-Bit Timer 5 Block Diagram
146
Table 25. TIMER 5 Register Map
146
12 Buzzer Driver
149
Buzzer Driver Block Diagram
149
Register Map
149
Figure 77. Buzzer Driver Block Diagram
149
Table 26. Buzzer Frequency at 8Mhz
149
Register Description
150
Table 27. Buzzer Driver Register Map
150
13 12-Bit ADC
151
Conversion Timing
151
Block Diagram
151
Figure 78. 12-Bit ADC Block Diagram
152
Figure 79. A/D Analog Input Pin with a Capacitor
152
Figure 80. A/D Power (AVREF) Pin with a Capacitor
152
ADC Operation
153
Figure 81. Control Registers and Align Bits
153
Register Map
154
Register Description
154
Figure 82. ADC Operation Flow Sequence
154
Table 28. ADC Register Map
154
Usi (Usart + Spi + I2C)
157
Usin UART Mode
157
Usin UART Block Diagram
158
Figure 83. Usin USART Block Diagram (N = 0 and 1)
158
Usin Clock Generation
159
Figure 84. Clock Generation Block Diagram (Usin)
159
Table 29. Equations for Calculating Usin Baud Rate Register Setting
159
Usin External Clock (Sckn)
160
Usin Synchronous Mode Operation
160
Usin UART Data Format
160
Figure 85. Synchronous Mode Sckn Timing (Usin)
160
Usin UART Parity Bit
161
Figure 86. Frame Formats (Usin)
161
Usin UART Transmitter
162
Usin UART Sending TX Data
162
Usin UART Transmitter Flag and Interrupt
162
Usin UART Parity Generator
163
Usin UART Disabling Transmitter
163
Usin UART Receiver
163
Usin UART Receiver RX Data
163
Usin UART Receiver Flag and Interrupt
164
Usin UART Parity Checker
164
Usin UART Disabling Receiver
164
Usin Asynchronous Data Reception
164
Figure 87. Asynchronous Start Bit Sampling (Usin)
165
Usin SPI Mode
166
Figure 88. Asynchronous Sampling of Data and Parity Bit (Usin)
166
Figure 89. Stop Bit Sampling and Next Start Bit Sampling (Usin)
166
Usin SPI Clock Formats and Timing
167
Figure 90. Usin SPI Clock Formats When Cphan = 0
167
Table 30. Cpoln Functionality
167
Figure 91. Usin SPI Clock Formats When Cphan = 1
168
Usin SPI Block Diagram
169
Usin I2C Mode
169
Figure 92. Usin SPI Block Diagram (N = 0 and 1)
169
Usin I2C Bit Transfer
170
Usin I2C Start/ Repeated Start/ Stop
170
Figure 93. Bit Transfer on the I2C-Bus (Usin)
170
Usin I2C Data Transfer
171
Usin I2C Acknowledge
171
Figure 94. START and STOP Condition (Usin)
171
Figure 95. Data Transfer on the I2C-Bus (Usin)
171
Usin I2C Synchronization/ Arbitration
172
Figure 96. Acknowledge on the I2C-Bus (Usin)
172
Usin I2C Operation
173
Figure 97. Clock Synchronization During Arbitration Procedure (Usin)
173
Figure 98. Arbitration Procedure of Two Masters (Usin)
173
Usin I2C Master Transmitter
174
Usin I2C Master Receiver
176
Usin I2C Slave Transmitter
177
Usin I2C Slave Receiver
178
Usin I2C Block Diagram
180
Register Map
180
Figure 99. Usin I2C Block Diagram
180
Table 31. USI Register Map
180
Usin Register Description
181
Baud Rate Settings (Example)
189
Table 32. Example1 of USI0BD and Usi1Bdsettings for Commonly Used Oscillator Frequencies
190
Table 33. Example2 of USI0BD and Usi1Bdsettings for Commonly Used Oscillator Frequencies
191
15 Usart2
192
Block Diagram
193
Figure 100. USART2 Block Diagram
193
Clock Generation
194
Figure 101. Clock Generation Block Diagram
194
Table 34. Equations for Calculating Baud Rate Register Setting
194
External Clock (XCK)
195
Synchronous Mode Operation
195
Figure 102. Synchronous Mode XCK Timing
195
Data Format
196
Figure 103. a Frame Format
196
Parity Bit
197
USART2 Transmitter
197
Sending Tx Data
197
Transmitter Flag and Interrupt
197
Parity Generator
198
Disabling Transmitter
198
USART2 Receiver
198
Receiving Rx Data
198
Receiver Flag and Interrupt
199
Parity Checker
199
Disabling Receiver
199
Asynchronous Data Reception
200
Figure 104. Start Bit Sampling
200
SPI Mode
201
Figure 105. Sampling of Data and Parity Bit
201
Figure 106. Stop Bit Sampling and Next Start Bit Sampling
201
SPI Clock Formats and Timing
202
Figure 107. SPI Clock Formats When UCPHA = 0
202
Table 35. CPOL Functionality
202
Figure 108. SPI Clock Formats When UCPHA = 1
203
Receiver Time out (RTO)
204
Figure 109. Example for RTO in USART2
204
Table 36. Example Condition of RTO
204
Register Map
205
Register Description
205
Table 37. USART2 Register Map
205
Baud Rate Settings (Example)
212
Table 38. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
212
0% Error Baud Rate
213
Figure 110. 0% Error Baud Rate Block Diagram
214
16 Power down Operation
215
Peripheral Operation in IDLE/ STOP Mode
215
Table 39. Peripheral Operation Status During Power down Mode
215
IDLE Mode
216
STOP Mode
216
Figure 111. IDLE Mode Release Timing by an External Interrupt
216
Released Operation of STOP Mode
217
Figure 112. STOP Mode Release Timing by External Interrupt
217
Register Map
218
Register Description
218
Figure 113. STOP Mode Release Flow
218
Table 40. Power down Operation Register Map
218
17 Reset
220
Reset Block Diagram
220
Power on Reset
220
Figure 114. Reset Block Diagram
220
Table 41. Hardware Setting Values in Reset State
220
Figure 115. Fast VDD Rising Time
221
Figure 116. Internal RESET Release Timing on Power-Up
221
Figure 117. Configuration Timing When Power-On
222
Figure 118. Boot Process Waveform
222
External Resetb Input
223
Table 42. Boot Process Description
223
Low Voltage Reset Process
224
Figure 119. Timing Diagram after RESET
224
Figure 120. Oscillator Generating Waveform Example
224
Figure 121. Block Diagram of LVR
225
Figure 122. Internal Reset at Power Fail Situation
225
LVI Block Diagram
226
Figure 123. Configuration Timing When LVR RESET
226
Figure 124. LVI Block Diagram
226
Register Map
227
Reset Operation Register Description
227
Table 43. Reset Operation Register Map
227
18 Memory Programming
230
Flash Control and Status Registers
230
Register Map
230
Register Description
230
Table 44. Flash Control and Status Register Map
230
Figure 125. Read Device Internal Checksum (Full Size)
235
Figure 126. Read Device Internal Checksum (User Define Size)
236
Memory Map
237
Flash Memory Map
237
Table 45. Program and Erase Time
237
Serial In-System Program Mode
238
Flash Operation
238
Figure 127. Flash Memory Map
238
Figure 128. Address Configuration of Flash Memory
238
Figure 129. the Sequence of Page Program and Erase of Flash Memory
239
Figure 130. the Sequence of Bulk Erase of Flash Memory
240
Mode Entrance Method of ISP Mode
244
Mode Entrance Method for ISP
244
Figure 131. ISP Mode
244
Table 46. Operation Mode
244
Table 47. Mode Entrance Method for ISP
244
Security
245
Configure Option
245
Table 48. Security Policy Using Lock Bits
245
19 Electrical Characteristics
248
Absolute Maximum Ratings
248
Table 49. Absolute Maximum Ratings
248
Recommended Operating Conditions
249
A/D Converter Characteristics
249
Table 50. Recommended Operating Conditions
249
Table 51. A/D Converter Characteristics
249
Power on Reset Characteristics
250
Low Voltage Reset and Low Voltage Indicator Characteristics
250
Table 52. Power-On Reset Characteristics
250
Table 53. LVR and LVI Characteristics
250
High Speed Internal RC Oscillator Characteristics
251
Low Speed Internal RC Oscillator Characteristics
251
Table 54. High Speed Internal RC Oscillator Characteristics
251
Table 55. Low Speed Internal RC Oscillator Characteristics
251
DC Characteristics
252
Table 56. DC Characteristics
252
AC Characteristics
253
Table 57. AC Characteristics
253
Figure 132. AC Timing
254
USART Characteristics
255
Table 58. USART Timing Characteristics in SYNC. or SPI Mode Operations
255
Figure 133. SPI Master Mode Timing (UCPHA = 0, MSB First)
256
Figure 134. Spi/Synchronous Master Mode Timing (UCPHA = 1, MSB First)
256
Figure 135 SPI Slave Mode Timing (UCPHA = 0, MSB First)
257
Figure 136 Spi/Synchronous Slave Mode Timing (UCPHA = 1, MSB First)
257
SPI0/1 Characteristics
258
Table 59. SPI0/1/2 Characteristics
258
UART0/1 Characteristics
259
Figure 137. SPI0/1/2 Timing
259
Table 60. UART0/1 Characteristics
259
I2C0/1 Characteristics
260
Figure 138. Waveform for UART0/1 Timing Characteristics
260
Figure 139. Timing Waveform for the UART0/1 Module
260
Table 61. I2C0/1 Characteristics
260
Data Retention Voltage in Stop Mode
261
Figure 140. I2C0/1 Timing
261
Table 62. Data Retention Voltage in Stop Mode
261
Internal Flash ROM Characteristics
262
Figure 141. Stop Mode Release Timing When Initiated by an Interrupt
262
Figure 142. Stop Mode Release Timing When Initiated by RESETB
262
Table 63. Internal Flash Rom Characteristics
262
Main Clock Oscillator Characteristics
263
Table 64. Main Clock Oscillator Characteristics
263
Sub-Clock Oscillator Characteristics
264
Figure 143. Crystal/Ceramic Oscillator
264
Figure 144. External Clock
264
Figure 145. Crystal Oscillator
264
Table 65. Sub Clock Oscillator Characteristics
264
Main Oscillation Stabilization Characteristics
265
Sub-Oscillation Characteristics
265
Figure 146. External Clock
265
Figure 147. Clock Timing Measurement at XIN
265
Table 66. Main Oscillation Stabilization Characteristics
265
Operating Voltage Range
266
Figure 148. Clock Timing Measurement at SXIN
266
Figure 149. Operating Voltage Range
266
Table 67. Sub Oscillation Stabilization Characteristics
266
Recommended Circuit and Layout
267
Typical Characteristics
267
Figure 150. Recommended Voltage Range
267
Figure 151. RUN (IDD1) Current
268
Figure 152. IDLE (IDD2) Current
268
Figure 153. STOP1 (IDD3) Current
269
Figure 154. Stop2 (IDD4) Current
269
20 Development Tools
270
Compiler
270
OCD (On-Chip Debugger) Emulator and Debugger
270
Figure 155. Debugger (OCD1/OCD2) and Pinouts
270
Programmers
271
OCD Emulator
271
Gang Programmer
271
Figure 156. E-PGM+ (Single Writer) and Pinouts
271
Flash Programming
272
On-Board Programming
272
Circuit Design Guide
272
Figure 157. E-Gang4 and E-Gang6 (for Mass Production)
272
Table 68. Pins for Flash Programming
272
On-Chip Debug System
273

Abov A96A148 User Manual (278 pages)

16 MHz 8-bit Microcontroller 64/32 Kbyte Flash memory, 12-bit ADC, 6 Timers, USART, USI, High Current Port

Brand: Abov | Category: Microcontrollers | Size: 3 MB

Introduction
1
Reference Document
1
Table of Contents
2
Description
13
Device Overview
13
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts
13
Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (Continued)
14
A96G140/A96G148/A96A148 Block Diagram
16
Figure 1. A96G140/A96G148/A96A148 Block Diagram
16
Pinouts and Pin Description
17
Pinouts
17
Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment
17
Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment
18
Figure 4. A96G140/A96G148 32LQFP Pin Assignment
19
Figure 5. A96G140/A96G148 32SOP Pin Assignment
20
Figure 6. A96G140/A96G148 28SOP Pin Assignment
20
Figure 7. A96A148 28SOP Pin Assignment
21
Pin Description
22
Table 3. Normal Pin Description
22
Port Structures
27
Figure 8. General Purpose I/O Port
27
Figure 9. External Interrupt I/O Port
28
Central Processing Unit (CPU)
29
Architecture and Registers
29
Figure 10. M8051EW Architecture
29
Addressing
31
Instruction Set
32
Memory Organization
34
Program Memory
34
Data Memory
35
Figure 11. Program Memory Map
35
Figure 12. Data Memory Map
36
External Data Memory
37
Figure 13. Lower 128Bytes of RAM
37
SFR Map
38
SFR Map Summary
38
Figure 14. XDATA Memory Area
38
Table 4. SFR Map Summary
38
Table 5. XSFR Map Summary
39
SFR Map
40
Table 6. SFR Map
40
Table 7. XSFR Map
44
Compiler Compatible SFR
45
O Ports
47
Port Register
47
Data Register (Px)
47
Direction Register (Pxio)
47
Pull-Up Register Selection Register (Pxpu)
47
Open-Drain Selection Register (Pxod)
47
Bounce Enable Register (Pxdb)
47
Port Function Selection Register (Pxfsr)
47
Register Map
48
Table 8. Port Register Map
48
P0 Port
49
P0 Port Description
49
Register Description for P0
49
P1 Port
52
P1 Port Description
52
Register Description for P1
52
P2 Port
56
P2 Port Description
56
Register Description for P2
56
P3 Port
58
P3 Port Description
58
Register Description for P3
58
P4 Port
60
P4 Port Description
60
Register Description for P4
60
P5 Port
62
P5 Port Description
62
Register Description for P5
62
Interrupt Controller
64
External Interrupt
65
Figure 15. Interrupt Group Priority Level
65
Block Diagram
66
Figure 16. External Interrupt Description
66
Figure 17. Interrupt Controller Block Diagram
67
Interrupt Vector Table
68
Table 9. Interrupt Vector Address Table
68
Interrupt Sequence
69
Effective Timing after Controlling Interrupt Bit
70
Figure 18. Interrupt Sequence Flow
70
Multi-Interrupt
71
Figure 19. Effective Timing of Interrupt Enable Register
71
Figure 20. Effective Timing of Interrupt Flag Register
71
Interrupt Enable Accept Timing
72
Figure 21. Effective Timing of Multi-Interrupt
72
Interrupt Service Routine Address
73
Saving/Restore General Purpose Registers
73
Figure 22. Interrupt Response Timing Diagram
73
Figure 23. Correspondence between Vector Table Address and the Entry Address of ISR
73
Figure 24. Saving/Restore Process Diagram and Sample Source
73
Interrupt Timing
74
Interrupt Register Overview
74
Interrupt Enable Register (IE, IE1, IE2, and IE3)
74
Interrupt Priority Register (IP and IP1)
74
Figure 25. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
74
External Interrupt Flag Register (EIFLAG0 and EIFLAG1)
75
External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1)
75
Register Map
75
Interrupt Register Description
75
Table 10. Interrupt Register Map
75
Clock Generator
82
Clock Generator Block Diagram
82
Register Map
83
Register Description
83
Figure 26. Clock Generator Block Diagram
83
Table 11. Clock Generator Register Map
83
Basic Interval Timer
86
BIT Block Diagram
86
BIT Register Map
86
Figure 27. Basic Interval Timer Block Diagram
86
Table 12. Basic Interval Timer Register Map
86
BIT Register Description
87
Watchdog Timer
88
WDT Interrupt Timing Waveform
88
Figure 28. Watch Dog Timer Interrupt Timing Waveform
88
WDT Block Diagram
89
Register Map
89
Register Description
89
Figure 29. Watch Dog Timer Block Diagram
89
Table 13. Watchdog Timer Register Map
89
Watch Timer
91
WT Block Diagram
91
Register Map
91
Figure 30. Watch Timer Block Diagram
91
Watch Timer Register Description
92
Table 14. Watch Timer Register Map
92
Timer 0/1/2/3/4/5
94
Timer 0
94
8-Bit Timer/Counter Mode
94
Table 15. Timer 0 Operating Mode
94
Figure 31. 8-Bit Timer/Counter Mode for Timer 0
95
Figure 32. 8-Bit Timer/Counter 0 Example
95
8-Bit PWM Mode
96
Figure 33. 8-Bit PWM Mode for Timer 0
96
Figure 34. PWM Output Waveforms in PWM Mode for Timer 0
97
8-Bit Capture Mode
98
Figure 35. 8-Bit Capture Mode for Timer 0
98
Figure 36. Input Capture Mode Operation for Timer 0
99
Figure 37. Express Timer Overflow in Capture Mode
99
Timer 0 Block Diagram
100
Register Map
100
Register Description
100
Figure 38. 8-Bit Timer 0 Block Diagram
100
Table 16. Timer 0 Register Map
100
Timer 1
102
16-Bit Timer/Counter Mode
102
Table 17. TIMER 1 Operating Modes
102
Figure 39. 16-Bit Timer/Counter Mode of Timer 1
103
Figure 40. 16-Bit Timer/Counter Mode Operation Example
103
16-Bit Capture Mode
104
Figure 41. 16-Bit Capture Mode of Timer 1
104
16-Bit PPG Mode
105
Figure 42. 16-Bit Capture Mode Operation Example
105
Figure 43. 16-Bit PPG Mode of Timer 1
106
Figure 44. 16-Bit PPG Mode Operation Example
107
16-Bit Timer 1 Block Diagram
108
Register Map
108
Register Description
108
Figure 45. 16-Bit Timer 1 Block Diagram
108
Table 18. TIMER 1 Register Map
108
Timer 2
111
16-Bit Timer/Counter Mode
112
Table 19. TIMER 2 Operating Modes
112
Figure 46. 16-Bit Timer/Counter Mode of Timer 2
113
16-Bit Capture Mode
114
Figure 48. 16-Bit Capture Mode of Timer 2
114
Figure 49. 16-Bit Capture Mode Operation Example
115
Figure 50. Express Timer Overflow in Capture Mode
115
16-Bit PPG Mode
116
Figure 51. 16-Bit PPG Mode of Timer 2
116
Figure 52. 16-Bit PPG Mode Operation Example
117
16-Bit Timer 2 Block Diagram
118
Register Map
118
Register Description
118
Figure 53. 16-Bit Timer 2 Block Diagram
118
Table 20. TIMER 2 Register Map
118
Timer 3
121
16-Bit Timer/Counter Mode
121
Table 21. TIMER 3 Operating Modes
121
Figure 47. 16-Bit Timer/Counter Mode Operation Example
122
Figure 54. 16-Bit Timer/Counter Mode of Timer 3
122
16-Bit Capture Mode
123
Figure 56. 16-Bit Capture Mode of Timer 3
123
Figure 57. 16-Bit Capture Mode Operation Example
124
Figure 58. Express Timer Overflow in Capture Mode
124
16-Bit PPG Mode
125
Figure 59. 16-Bit PPG Mode of Timer 3
125
Figure 60. 16-Bit PPG Mode Operation Example
126
16-Bit Timer 3 Block Diagram
128
Register Map
128
Register Description
128
Figure 61. 16-Bit Timer 3 Block Diagram
128
Table 22. TIMER 3 Register Map
128
Timer 4
131
16-Bit Timer/Counter Mode
132
Table 23. TIMER 4 Operating Modes
132
Figure 55. 16-Bit Timer/Counter Mode Operation Example
133
Figure 62. 16-Bit Timer/Counter Mode of Timer 4
133
16-Bit Capture Mode
134
Figure 64. 16-Bit Capture Mode of Timer 4
134
Figure 65. 16-Bit Capture Mode Operation Example
135
Figure 66. Express Timer Overflow in Capture Mode
135
16-Bit PPG Mode
136
Figure 67. 16-Bit PPG Mode of Timer 4
136
Figure 68. 16-Bit PPG Mode Operation Example
137
16-Bit Timer 4 Block Diagram
138
Register Map
138
Register Description
138
Figure 69. 16-Bit Timer 4 Block Diagram
138
Table 24. TIMER 4 Register Map
138
Timer 5
141
16-Bit Timer/Counter Mode
141
Table 25. TIMER 5 Operating Modes
141
Figure 63. 16-Bit Timer/Counter Mode Operation Example
142
Figure 70. 16-Bit Timer/Counter Mode of Timer 5
142
Figure 71. 16-Bit Timer/Counter Mode Operation Example
142
16-Bit Capture Mode
143
Figure 72. 16-Bit Capture Mode of Timer 5
143
16-Bit PPG Mode
144
Figure 73. 16-Bit Capture Mode Operation Example
144
Figure 74. Express Timer Overflow in Capture Mode
144
Figure 75. 16-Bit PPG Mode of Timer 5
145
Figure 76. 16-Bit PPG Mode Operation Example
146
16-Bit Timer 5 Block Diagram
147
Register Map
147
Register Description
147
Figure 77. 16-Bit Timer 5 Block Diagram
147
Table 26. TIMER 5 Register Map
147
Buzzer Driver
150
Buzzer Driver Block Diagram
150
Register Map
150
Figure 78. Buzzer Driver Block Diagram
150
Table 27. Buzzer Frequency at 8Mhz
150
Register Description
151
Table 28. Buzzer Driver Register Map
151
12-Bit ADC
152
Conversion Timing
152
Block Diagram
152
Figure 79. 12-Bit ADC Block Diagram
153
Figure 80. A/D Analog Input Pin with a Capacitor
153
Figure 81. A/D Power (AVREF) Pin with a Capacitor
153
ADC Operation
154
Figure 82. Control Registers and Align Bits
154
Register Map
155
Register Description
155
Figure 83. ADC Operation Flow Sequence
155
Table 29. ADC Register Map
155
Usi (Usart + Spi + I2C)
158
Usin UART Mode
158
Usin UART Block Diagram
159
Figure 84. Usin USART Block Diagram (N = 0 and 1)
159
Usin Clock Generation
160
Figure 85. Clock Generation Block Diagram (Usin)
160
Table 30. Equations for Calculating Usin Baud Rate Register Setting
160
Usin External Clock (Sckn)
161
Usin Synchronous Mode Operation
161
Usin UART Data Format
161
Figure 86. Synchronous Mode Sckn Timing (Usin)
161
Usin UART Parity Bit
162
Figure 87. Frame Formats (Usin)
162
Usin UART Transmitter
163
Usin UART Sending TX Data
163
Usin UART Transmitter Flag and Interrupt
163
Usin UART Parity Generator
164
Usin UART Disabling Transmitter
164
Usin UART Receiver
164
Usin UART Receiver RX Data
164
Usin UART Receiver Flag and Interrupt
165
Usin UART Parity Checker
165
Usin UART Disabling Receiver
165
Usin Asynchronous Data Reception
165
Figure 88. Asynchronous Start Bit Sampling (Usin)
166
15.10 Usin SPI Mode
167
Figure 89. Asynchronous Sampling of Data and Parity Bit (Usin)
167
Figure 90. Stop Bit Sampling and Next Start Bit Sampling (Usin)
167
15.11 Usin SPI Clock Formats and Timing
168
Figure 91. Usin SPI Clock Formats When Cphan = 0
168
Table 31. Cpoln Functionality
168
Figure 92. Usin SPI Clock Formats When Cphan = 1
169
15.12 Usin SPI Block Diagram
170
15.13 Usin I2C Mode
170
Figure 93. Usin SPI Block Diagram (N = 0 and 1)
170
15.14 Usin I2C Bit Transfer
171
15.15 Usin I2C Start/ Repeated Start/ Stop
171
Figure 94. Bit Transfer on the I2C-Bus (Usin)
171
15.16 Usin I2C Data Transfer
172
15.17 Usin I2C Acknowledge
172
Figure 95. START and STOP Condition (Usin)
172
Figure 96. Data Transfer on the I2C-Bus (Usin)
172
15.18 Usin I2C Synchronization/ Arbitration
173
Figure 97. Acknowledge on the I2C-Bus (Usin)
173
15.19 Usin I2C Operation
174
Figure 98. Clock Synchronization During Arbitration Procedure (Usin)
174
Figure 99. Arbitration Procedure of Two Masters (Usin)
174
Usin I2C Master Transmitter
175
Usin I2C Master Receiver
177
Usin I2C Slave Transmitter
178
Usin I2C Slave Receiver
179
15.20 Usin I2C Block Diagram
181
15.21 Register Map
181
Figure 100. Usin I2C Block Diagram
181
Table 32. USI Register Map
181
15.22 Usin Register Description
182
Baud Rate Settings (Example)
190
Table 33. Example1 of USI0BD and Usi1Bdsettings for Commonly Used Oscillator Frequencies
191
Table 34. Example2 of USI0BD and Usi1Bdsettings for Commonly Used Oscillator Frequencies
192
Usart2
193
Block Diagram
194
Figure 101. USART2 Block Diagram
194
Clock Generation
195
Figure 102. Clock Generation Block Diagram
195
Table 35. Equations for Calculating Baud Rate Register Setting
195
External Clock (XCK)
196
Synchronous Mode Operation
196
Figure 103. Synchronous Mode XCK Timing
196
Data Format
197
Figure 104. a Frame Format
197
Parity Bit
198
USART2 Transmitter
198
Sending Tx Data
198
Transmitter Flag and Interrupt
198
Parity Generator
199
Disabling Transmitter
199
USART2 Receiver
199
Receiving Rx Data
199
Receiver Flag and Interrupt
200
Parity Checker
200
Disabling Receiver
200
Asynchronous Data Reception
201
Figure 105. Start Bit Sampling
201
SPI Mode
202
Figure 106. Sampling of Data and Parity Bit
202
Figure 107. Stop Bit Sampling and Next Start Bit Sampling
202
SPI Clock Formats and Timing
203
Figure 108. SPI Clock Formats When UCPHA = 0
203
Table 36. CPOL Functionality
203
Figure 109. SPI Clock Formats When UCPHA = 1
204
Receiver Time out (RTO)
205
Figure 110. Example for RTO in USART2
205
Table 37. Example Condition of RTO
205
16.11 Register Map
206
16.12 Register Description
206
Table 38. USART2 Register Map
206
Baud Rate Settings (Example)
214
Table 39. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
214
16.14 0% Error Baud Rate
215
Figure 111. 0% Error Baud Rate Block Diagram
216
Power down Operation
217
Peripheral Operation in IDLE/ STOP Mode
217
Table 40. Peripheral Operation Status During Power down Mode
217
IDLE Mode
218
STOP Mode
218
Figure 112. IDLE Mode Release Timing by an External Interrupt
218
Released Operation of STOP Mode
219
Figure 113. STOP Mode Release Timing by External Interrupt
219
Register Map
220
Register Description
220
Figure 114. STOP Mode Release Flow
220
Table 41. Power down Operation Register Map
220
Reset
222
Reset Block Diagram
222
Power on Reset
222
Figure 115. Reset Block Diagram
222
Table 42. Hardware Setting Values in Reset State
222
Figure 116. Fast VDD Rising Time
223
Figure 117. Internal RESET Release Timing on Power-Up
223
Figure 118. Configuration Timing When Power-On
224
Figure 119. Boot Process Waveform
224
External Resetb Input
225
Table 43. Boot Process Description
225
Low Voltage Reset Process
226
Figure 120. Timing Diagram after RESET
226
Figure 121. Oscillator Generating Waveform Example
226
Figure 122. Block Diagram of LVR
227
Figure 123. Internal Reset at Power Fail Situation
227
LVI Block Diagram
228
Figure 124. Configuration Timing When LVR RESET
228
Figure 125. LVI Block Diagram
228
Register Map
229
Reset Operation Register Description
229
Table 44. Reset Operation Register Map
229
Memory Programming
232
Flash Control and Status Registers
232
Register Map
232
Table 45. Flash Control and Status Register Map
232
Register Description
233
Figure 126. Read Device Internal Checksum (Full Size)
237
Figure 127. Read Device Internal Checksum (User Define Size)
238
Memory Map
239
Flash Memory Map
239
Table 46. Program and Erase Time
239
Serial In-System Program Mode
240
Flash Operation
240
Figure 128. Flash Memory Map
240
Figure 129. Address Configuration of Flash Memory
240
Figure 130. the Sequence of Page Program and Erase of Flash Memory
241
Figure 131. the Sequence of Bulk Erase of Flash Memory
242
Mode Entrance Method of ISP Mode
246
Mode Entrance Method for ISP
246
Figure 132. ISP Mode
246
Table 47. Operation Mode
246
Table 48. Mode Entrance Method for ISP
246
Security
247
Configure Option
247
Development Tools
250
Compiler
250
Core and Debug Tool Information
251
Feature of 94/96/97 Series Core
251
OCD Type of 94/96/97 Series Core
253
Interrupt Priority of 94/96/97 Series Core
254

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