Theory Of Operation - Analog Devices DC2874A-A Demo Manual

THEORY OF OPERATION

Introduction to the DC2874A
The DC2874A demonstration circuit features the LTC3310S,
a Low Voltage Synchronous Step-Down Silent Switcher in
two, three, or four phase operation. The LTC3310S is a
monolithic, constant frequency, current mode step-down
DC/DC converter. Connecting the RT pin of the master
phase, to a resistor to AGND programs the frequency from
500kHz to 2.25MHz and configures the MODE/SYNC pin
to become clock output used to drive the MODE/SYNC pin
of the slave phase(s). The DC2874A can operate with an
external clock by shorting the master phase RT pin to V
by placing a 0Ω resistor in the R5 location and applying a
sync pulse on the MODE/SYNC turret.
Connecting the FB pin to V
slave. The MODE/SYNC becomes an input and the voltage
control loop is disabled. The slave phase current control
loop is still active and the peak current is controlled via the
shared ITH node. The phasing of a slave phase relative to
the master phase is programmed with a resistor divider
on the RT pin. Refer to Table 5 of the LT3310S datasheet
for more information on setting the slave phase angle.
In the multiphase application the LTC3310S operate in
pulse skip mode. At light loads, the slave phases will start
pulse skipping before the master phase and can eventu-
ally stop switching as the load continues to decrease.
The ability to allow the slave phases to stop switching
at light loads reduces Iq current and switching losses at
light loads.
Setting the compensation for the multiphase is similar to
setting the compensation to a single phase. When deter-
mining the compensation components, C11, C14 and R8,
controlling the loop stability and transient response are
the two main considerations. The LTC3310S has been
configures a phase as a
IN
DEMO MANUAL DC2874A-A/
DC2874A-B/DC2874A-C
designed to operate at a high bandwidth for fast transient
response capabilities. This reduces output capacitance
required to meet the desired transient voltage range. The
mid-band gain of the loop increases with R8 and the band-
width of the loop increases with decreasing C14. C11
along with R6 provides a phase lead which will improve
the phase margin. C13, C33, C34, and C44 along with
R12 provides a high frequency pole to reduce the high
frequency gain. C13, C33, C34, and C44 are in paral-
lel on the ITH node. The sum of these caps will be the
total capacitance on the Master phase ITH pin. Too much
IN
capacitance can slow down the response time.
Loop stability is generally measured using the Bode Plot
method of plotting loop gain in dB and phase shift in
degrees. The 0dB crossover frequency should be less
the 1/6 of the operating frequency to reduce the effects
of added phase shift of the modulator. The control loop
phase margin goal should be 45°. or greater and a gain
margin goal of 8dB or greater. Refer to the LTC3310S
datasheet and LTPowerCAD
choosing the required components.
The softstart of the multiphase regulator is controlled by a
single cap, C12, on the master phase. After the regulator
is in regulation the SSTT pin can be used to monitor the
temperature of each IC. The master phase temperature
can be monitored at the SSTT turret and slave 1, 2, and 3
can be monitored at TP3, 4, and 6 respectively. Calculate
the die temperature with the formula below:
V
SSTT
T (°C ) = − 237
J
4mV
for more information on
(3)
Rev. 0
5