National Instruments NI 447 Series User Manual page 46

Chapter 3 Device Overview and Theory of Operation
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NI 447X User Manual
at exactly the same time. Figure 3-13 illustrates the oversample pulse trains
on two NI 447X devices sampling at 102.4 kS/s. In this example, there is a
delay between acquisition samples of five oversample intervals, or about
350 ns. This delay may be any value up to a whole sample interval, which
is about 10 µs at this acquisition rate.
t
Data Returned
p
Figure 3-13. Sample Delay between NI 447X Modules After Receiving a Shared
The solution to the clock-delay issue is to configure the master device to
issue a SYNC pulse before the acquisition. The clock master sends a single
active low, or inverted, pulse on the RTSI 5/TRIG 5 line, the dedicated line
for the SYNC pulse. The ADCs in the clock master and clock slaves receive
this pulse nearly simultaneously. The SYNC pulse forces all the ADCs to a
reset state, emptying their digital filters and synchronizing their clock
dividers. After exiting the reset state, all NI 447X modules run at the same
frequency and have minimal phase difference between sample clocks.
Figure 3-14 illustrates how this technique minimizes the sample delay.
Sample Delay ≈ 350 ns
≈ 70 ns
t
p
Oversample Clock
3-16
Data Returned
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