Power Inductor - Infineon AIROC CYW20835 User Manual

AIROC™ CYW20835 Bluetooth® LE system on chip hardware design
guidelines
Component placement
VDDIO to LHL_VDDO (pin 60)/BT_VDDO (pin 36) → Minimum 8 mils trace width
−
BT_VDDC → Minimum 10 mils trace width
−
BT_VDDC (pin 37) → Minimum 8 mils trace width
−
VBAT to SR_VDDBAT3V (pin 22) → Minimum 12 mils trace width
−
CBUCK_OUT to RFLDOIN (pin 24) → Minimum 8 mils trace width
−
RFLDO_VDDOUT (pin 12) to 1P2VRF → Minimum 8 mils trace width
−
VPA_BT → Minimum 12 mils trace width
−
PALDO_VDDOUT3V (pin 20) to BT_PAVDD2P5 (pin 26) → Minimum 8 mils trace width
−
1P2VRF → Minimum 8 mils trace width
−
1P2VRF to IFVDD1P2 (pin 19)/PLLVDD1P2 (pin 21) / VCOVDD1P2 (pin 20) → Minimum 8 mils trace width
−
MIC_AVDD (pin 48) → Minimum 8 mils trace width
−
MIC_BIAS (pin 45) → Minimum 8 mils trace width
−
Figure 5 Power supply traces
2.12

Power inductor

Ensure that there is ground isolation between the power inductor and the RF area. The power inductor should
also be placed as close to CBUCK pins as possible. See the "Recommended component" section in the
CYW20835 datasheet, and reference design files for the recommended component.
User Guide 7 of 11 002-34024 Rev. **
2021-10-05