Intel Core Duo Mobile 945GM User Manual page 29

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Optional on-die voltage regulator
Information on Intel® Active Management Technology can be found at:
http://www.intel.com/technology/manage/iamt/
3.4.2.4 AC'97 and High Definition Audio
AC'97 and Intel
3.4.2.5 ATA / Storage
®
The Intel
connectors. The parallel ATA IDE Connector is a standard 40-pin connector at J7J1 for a desktop
IDE drive. A power connector is supplied on the platform to power a parallel ATA hard disk drive
at J4J2. One of the two serial ATA connectors on the Intel
connect connector; located at J8J2. The other serial ATA connector is broken up into two
connectors. One connector is for the serial data signals, and the other is to power the serial ATA
hard disk drive. These connectors are located at J7H1 and J6H3. A green LED at location CR7J1
indicates activity on the ATA channel.
®
The Intel
channel and the serial ATA channels. A device can be powered down by software and the port can
then be disabled, allowing removal and insertion of a new device. The parallel IDE device should
be powered from the power connector, J4J2, on the Intel
hot swap feature. This feature requires customer-developed software support.
Desktop hard drives must be powered using the external ATX power supply, not the onboard power
supply.
®
The Intel
performance and reliability through features such as Native Command Queuing (NCQ) and RAID
0/1. For more information about Intel® Matrix Storage Technology, refer to Intel's website at:
http://www.intel.com/design/chipsets/matrixstorage_sb.htm
3.4.2.6 USB Connectors
The ICH7-M provides a total of eight USB 2.0 ports. Three ports are routed to a triple-stack USB
connector at J3A1. Two ports are routed to a combination RJ-45/dual USB connector at J5A1B.
Three ports are routed to USB front panel headers at J6H2 and J7E2.
3.4.2.7 LPC Super I/O (SIO)/LPC Slot
An SMSC LPC47N207 serves as the SIO on the Intel
Shunting the jumper at J7E3 to the 2-3 positions can disable the SIO by holding it in reset. This
allows other SIO solutions to be tested in the LPC slot at J8F1. A sideband header is provided at
J9G2 for this purpose. This sideband header also has signals for LPC power management.
Information on this header is on sheet 35 of the Intel
detailed in the "LPC Slot and Sideband Header Specification" (see
on page 15).
®
Mobile Intel 945GM Express Chipset
Development Kit User's Manual
®
High Definition Audio are not supported on the board.
945GM Express Chipset provides one parallel ATA IDE connector and two serial ATA
945GM Express Chipset also supports 'ATA swap' capability for both the parallel IDE
945GM Express Chipset includes Intel® Matrix Storage Technology, providing greater
Theory of Operation
®
945GM Express Chipset is a direct
®
945GM Express Chipset to utilize the
®
945GM Express Chipset platform.
®
945GM Express Chipset schematics and is
Table 3, "Related Documents"
29