Theory of Operation
•
ACPI* 2.0 compliant
•
Real Time Clock
•
652 mBGA package
•
Two SATA drive connectors
•
One IDE connector
•
Eight Universal Serial Bus (USB) 2.0 ports (five ports provided on rear-panel, three provided
via headers (J6H2, J7E2)
3.4.2.1
PCI Express* Slots
The reference board has two x1 PCI Express* slots for add-in cards. The PCI Express* interface is
compliant to the PCI Express* Rev. 1.0a Specification.
3.4.2.2
PCI Slots
The reference board has two PCI slots for add-in cards. The PCI bus is compliant to the PCI Rev.
2.3 Specification at 33 MHz.
3.4.2.3
On-Board LAN
The 82573E provides the LAN connectivity for this platform. It provides Gigabit ethernet as well
as Intel® Active Management Technology functions. It is connected to the ICH7-M through a PCIe
interface and to an RJ45 connector at J5A1A with built in magnetic decoupling. Access to this
interface is provided on the rear I/O panel (See
Features of the 82573E are as follows:
•
x1 PCIe Interface
•
2 Gbps peak bandwidth per direction
•
Wide, pipelined internal data path architecture
•
32 KB configurable Receive (Rx) and Transmit (Tx) FIFO
•
IEEE 802.3x compliant flow control support with software controllable pause times and
threshold values
•
Programmable host memory Rx buffers (256 B- 16 KB)
•
Descriptor ring management hardware for Tx and Rx
•
Tx/Rx IP, TCP, and UDP checksum offloading
•
Tx TCP Segmentation
•
IPv6 offloading
•
IEEE 802.1g virtual LAN support
•
Intel® Active Management Technology
•
Wake on LAN (WoL) support
Note: The 82573E is only powered in S3-S0 and will not support AMT or WoL support from S4 or S5.
•
SPI or EEPROM support
28
Figure 3 on page
42).
®
Mobile Intel
Development Kit User's Manual
945GM Express Chipset