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Input Board (Ipm-77) - Sony CSP-5000E Service Manual

System controller, input board, output board, system keyboard
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[Sync control block]
• The signal generator IC CXD1159Q (IC509) produces
composite sync signals.
• This block synchronizes the composite signals with
external signals. The block diagram of the sync signal
circuit is given below.
SYNC CONTROL BLOCK
OSC
14 MH
Z
VOC
PHASE
AC LINE
SHAPING
ADJ.
IC501 BA7046F
SYNC
PHASE
SYNC IN
SEP.
ADJ.
SYNC OUT
CPU
IC113 MC68HC11M0
SW501
INT/LL

INPUT BOARD (IPM-77)

VD/PTZ
REFERENCE
VOLTAGE
VD-S PULSE
PTZ-DATA
SYNC CHIP LEVEL
+
CLAMP
VIDEO+VD+PTZ
5-6
IC512 SN74HC125
FLD (VD/2)
VD
SG
IC509 CXD1159Q
HD
C.SYNC
PHASE
COMP.
IC506 TC8081AP
IC507 CX20158
VD-S PULSE
VD-S CANCEL
PTZ-DATA
PTZ-DATA CANCEL
VD/PTZ CANCEL
CABLE COMP
VIDEO
Input Board (IPM-77)
Operation
• Installed in the CPS-5000E, the board provides the
following functions:
1 To send multiple sync signals (VD-S),
2 To send PTZ (panning, tilting, lens) control data,
3 To compensate for cable losses
4 To function as matrix switch
• The input video signals from CN13 are terminated by
R103 (75 Ω) and forwarded to add to the VD-S pulse
and the PTZ control data at the blanking periods. The
height of those pulse and data is adjusted in two steps by
the IC HC4052 (IC109), depending upon cable length.
• The video signals, combined with the VD-S pulse and
the PTZ control data, are sent through an emitter-
follower circuit to the IC ADG512 (IC108), where
IC108 restores the combined signals into the video
signals at an original signal level. The video signals are
then compensated for loss due to the cable and
forwarded to the sync separator and the clamp circuit
simultaneously.
• In the sync separator circuit, the VD, HD, and C. Sync
signals are extracted from the video signals and sent to
the PLD (IC32), where IC32 synchronizes them with the
PTZ control data.
• In the clamp circuit, the video signals are forwarded to
the IC MAX465 (IC76-IC79), where their output level is
adjusted to the specified level, and further sent to CN13.
VD
VD-S PULSE
VD ON/OFF
PLD
CPU
SYNC SEP
CLAMP
MATRIX SW
X8
MOTHER BOARD BUS
SW/PTZ-DATA
AT-BUS
DRAM
LOCAL BUS
VIDEO
X32
CSP-5000E
CSPK-5000E

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Cspb-51ovcCspb-520vcCspk-5000e