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Circuit Description
Main Control Board (CPU-185)
Outline
• The CPU-185 board mainly acts as the central control
section for data communication and for the data
processing section to communicate with the system
keyboard.
• The board consists of the following blocks:
[PC block (AT)]
• This block controls data communication for the total
CSP-5000E system and data processing for various
system controls.
• It consists of a central unit, the CPU module (card PC)
installed in CN601, the RS-232C driver/receiver
µ PD4724 (IC626, IC631), the printer buffer
TC74ACT245 (IC633), the buzzer (BZ601), the reset/
power supply sensor IC S-80754 (IC606), and the 3.3V
power supply regulator LT1086 (IC604).
• This block communicates with Keyboard IF block
(KBIF), which is another block on the CPU-185 board,
the input board (IPM-77), the output board (OPM-11),
and the switch control board (CT), through the PC bus
(CN606).
• With S601 on the CPU-185 board depressed, the block
resets the total operation of the CSP-5000E by sending
the reset control signal to the entire system.
• The card PC installed in the CPU-185 board, is PC/AT
compatible. Therefore, the CSP-5000E is equipped with
the RS-232C(two lines), the printer port, the PS2
keyboard port, the PS2 mouse port, and the VGA
monitor port, as extension connectors. However, they are
currently not used.
• The programs for operating the card PC are written in
the FLASH ROM in the card PC.
[Keyboard IF Block (KBIF)]
• This block communicates with the system keyboard,
model CSPK-5000E, and transfers data into the PC
block (AT) or processes data by itself, if required.
Similarly, the block communicates with the PC block
(AT), and transfers data into the CSPK-5000E or
processes data by itself.
CSP-5000E
CSPK-5000E
• The block consists of a central unit, the 8-bit CPU
MC68HC11M0CFU4 (IC630), the dual port RAM
MB8421 (IC618), which is used for communication with
the PC block (AT), buffers to interconnect with the PC
bus, the data communication control IC PC16552DV
(IC617, IC623, IC629, IC635), EPROM MC27C1001
(IC634), the data backup RAM CXK-58257 (IC639), the
RS-422 driver/receiver SN75ALS1178 (IC614, IC619,
IC621, IC624), and decoders for choosing devices.
• The interfaces with the data communication control IC,
and with the PC block (AT) are established as priority
processing. The data communication control IC sends
priority signals to each of the keyboard interfaces,
resulting in priority interfaces of eight or less. Those
interfaces may handle communication errors as well as
sending/receiving data, however, the CPU processes
them appropriately. The interface with the PC block
(AT) is established by sending to the CPU XIRQ
terminal the reversed rise signal of the VD/2, which is in
sync with video frames and supplied from the bus
through CN606. In other words, the interface begins
immediately after the rise signal of the VD/2 is given.
• The CPU (IC630) has the program capacity of 32k bytes,
and the program is written in the EPROM (IC634). The
EPROM has four program capacities, 32k bytes each,
and its bank is selected by the dip switch (S602). For the
CPS-5000E, only bank #2 is used; the other banks
contain no programs. (S602 #2 is ON, the others OFF)
[Battery backup block]
• This block holds the SRAM (IC639), consisting of the
lithium battery CR2032 (BT601), the power supply
switch (Q603, Q604), the battery check switch (Q606,
Q607), and the reverse current prevention circuit.
• The CPU (IC630) continuously watches the battery
power remaining in the lithium battery, and sends its
data to the PC block (AT), which in turn sends the
CSPK-5000E's LCD commands to indicate a warning
when the battery power becomes less than specified.
• The lithium battery holds the setting memory for the
card PC and the SRAM (IC639) in which the
CSP-5000E's (partial) operation is set.
5-3
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