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The recommended voltage range on the VC0 to VC4 pins extends to –0.2 V. This can be used, for example,
to measure a differential voltage that extends slightly below ground, such as the voltage across a second
sense resistor in parallel with that connected to the SRP and SRN pins.
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If a system does not use high-side protection FETs, then the PACK pin can be connected through a series
10-kΩ resistor to the top of stack. The LD pin can be connected to VSS. In this case, the LD pin can also be
controlled separately, in order to wake the device from SHUTDOWN mode, such as through external circuitry
which holds the LD pin at the voltage of VSS while the device stays in SHUTDOWN, and to be driven above
a voltage of V
WAKEONLD
•
TI recommends using 100 Ω resistors in series with the SRP and SRN pins, and a 100 nF with optional 100
pF differential filter capacitance between the pins for filtering. The routing of these components, together with
the sense resistor, to the pins should be minimized and fully symmetric, with all components recommended to
stay on the same side of the PCB with the device. Capacitors should not be connected from the pins to VSS.
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Due to thermistors often being attached to cells and possibly needing long wires to connect back to the
device, it may be helpful to add a capacitor from the thermistor pin to the device VSS. However, it is important
to not use too large of a value of capacitor, since this will affect the settling time when the thermistor is
biased and measured periodically. A rule of thumb is to keep the time constant of the circuit < 5% of the
measurement time. When Settings:Configuration:Power Config[FASTADC] = 0, the measurement time is
approximately 3 ms, and with [FASTADC] = 1 the measurement time is halved to approximately 1.5 ms.
When using the 18 kΩ pullup resistor with the thermistor, the time constant will generally be less than (18 kΩ)
× C, so a capacitor less than 4 nF is recommended. When using the 180-kΩ pullup resistor, the capacitor
should be less than 400 pF.
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The integrated charge pump generates a voltage on the CP1 capacitor, requiring approximately 60 ms to
charge up to approximately 11 V when first enabled, when using the recommended 470 nF capacitor value.
When the CHG or DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the CHG
and DSG capacitive FET loads. This will generally result in a brief drop in the voltage on CP1, which is then
replenished by the charge pump. If the FET capacitive loading is large, such that at FET turn-on the voltage
on CP1 drops below an acceptable level for the application, then the value of the CP1 capacitor can be
increased. This has the drawback of requiring a longer startup time for the voltage on CP1 when the charge
pump is first powered on, and so should be evaluated to ensure it is acceptable in the system. For example,
if the CHG and DSG FETs are enabled simultaneously and their combined gate capacitance is approximately
400 nF, then changing CP1 to a value of 2200 nF will result in the 11-V charge pump level dropping to
approximately 9 V, before being restored to the 11-V level by the charge pump.
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in order to wake from SHUTDOWN.
Product Folder Links:
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
BQ76952
BQ76952
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