Startup Timing - Texas Instruments 3 Series Manual

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should generally be floating before they are connected to the appropriate cell. It is expected that transient
current will flow briefly when each cell is attached, but the cell voltages will quickly stabilize to a state without
DC current flowing through the diodes. However, if a large capacitance is included between a cell input pin
and another terminal (such as VSS or another cell input pin), the transient current may become excessive
and lead to device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin
to the values recommended in the specifications.

16.4 Startup Timing

At initial power up of the BQ76952 device from a SHUTDOWN state, the device progresses through a sequence
of events before entering NORMAL mode operation. These are described below for an example configuration,
with approximate timing shown for the cases when [FASTADC] = 0 and [FASTADC] = 1.
When the device is configured for autonomous FET control (that is, [FET_EN] = 1), the decision to
enable FETs is only evaluated every 250 ms while in NORMAL mode, which is why the FETs are
not enabled until approximately 280 ms after the wakeup event, even though the data was available
earlier.
Step
Wakeup event
REG1 powered
INITSTART asserted
INITCOMP and ADSCAN
asserted
FULLSCAN asserted
FETs enabled
Figure 16-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP
with [FASTADC] = 1, [FET_EN] = 1 for autonomous FET control, setup to use three thermistors, and providing
the [INITCOMP] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.
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Table 16-2. Startup Sequence and Timing
Comment
Either the TS2 pin is pulled
low, or the LD pin is pulled
up, triggering the device to exit
SHUTDOWN mode.
This was measured with the OTP
programmed to autonomously
power the REG1 LDO.
This was measured with the
OTP programmed to provide the
INITSTART bit in the Alarm signal
on the ALERT pin.
This was measured with the
OTP programmed to provide the
INITCOMP and ADSCAN bits in
the Alarm signal on the ALERT
pin.
This was measured with the
OTP programmed to provide the
FULLSCAN bit in the Alarm
signal on the ALERT pin.
This was measured with the OTP
programmed to autonomously
enable FETs.
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SLUSE13A – JANUARY 2020 – REVISED MAY 2021
Note
FASTADC Setting
0, 1
0, 1
0, 1
0
1
0
1
0
1
BQ76952
BQ76952
Time (relative to wakeup event)
0
20 ms
23 ms
88 ms
58 ms
221 ms
129 ms
282 ms
284 ms
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