Texas Instruments 3 Series Manual page 55

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The CRC polynomial is x
When the responder detects an invalid CRC, the I
responder to go to an idle state.
SCL
A7 A6
SDA
Start
2
I C Read with Repeated Start
SCL
SDA A7 A6
Start
2
I C Read without Repeated Start
not available in hardware. For a block read, the controller ACKs each data byte except the last and continues to
clock the interface. The I
When enabled, the CRC for a read transaction is calculated as follows:
• In a single-byte read transaction, the CRC is calculated beginning at the first start, so includes the responder
address, the register address, then the responder address with a read bit set, then the data byte.
• In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will
include the responder address, the register address, then the responder address with a read bit set, then the
data byte. The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is
calculated over the data byte only.
The CRC polynomial is x
When the controller detects an invalid CRC, the I
responder to go to an idle state.
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8 2
+ x + x + 1, and the initial value is 0.
...
A1 R7 R6
R/W ACK
Responder Register
Address
Address
Figure 14-1. I
shows a read transaction using a Repeated Start.
...
A1 R7 R6
R/W ACK
Register
Responder
Address
Address
2
Figure 14-2. I C Read with Repeated Start
shows a read transaction where a Repeated Start is not used; for example, if
2
C block auto-increments the register address after each data byte.
8 2
+ x + x + 1, and the initial value is 0.
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2
C responder NACKs the CRC, which causes the I
... ...
R0 D7 D6 D0
ACK ACK
Data
2
C Write
... ...
R0 A7 A6 A1
ACK
Responder
Address
Repeated
Start
...
D7 D6 D0
ACK
Responder
Drives Data
2
C controller will NACK the CRC, which causes the I
BQ76952
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
...
C7 C6 C0
ACK
CRC
Stop
(optional)
R/W ACK
...
C7 C6 C0
NACK
Respsonder
Stop
Drives CRC
(optional )
Controller
Drives NACK
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BQ76952
2
C
2
C
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