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Typical values stated where T
to 80 V (unless otherwise noted)
PARAMETER
Input voltage range
V
(divider measurement
(ADC_IN_DIV)
mode)
Integral nonlinearity
(when using V
and differential cell
B
(ADC_INL)
voltage measurement
mode at VC16 -
VC15)
Differential
B
(ADC_DNL)
nonlinearity
Differential cell offset
B
(ADC_OFF_CELL)
error
B
ADCIN offset error
(ADC_OFF)
B
Divider offset error
(ADC_OFF_DIV)
Differential cell offset
B
(ADC_OFF_DRIFT_CELL)
error drift
B
Gain
(ADC_GAIN)
B
Gain drift
(ADC_GAIN_DRIFT)
Effective input
R
(ADC_IN_CELL)
resistance
Effective input
R
(ADC_IN_LD)
resistance
Effective input
R
(ADC_IN_DIV)
resistance
B
Code stability
(ADC_RES)
Code stability in fast
B
(ADC_RES_FAST)
(2)
mode
t
Conversion-time
(ADC_CONV)
Conversion-time in
t
(ADC_CONV_FAST)
fast mode
(1)
Operation with V
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
BAT
5.5 V or 11 V mode), the maximum voltage on V
their maximum specified voltage.
(2)
Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.
(3)
Specified by design
(4)
Specified by characterization
Copyright © 2021 Texas Instruments Incorporated
= 25°C and V
= 59.2 V, min/max values stated where T
A
BAT
(1)
TEST CONDITIONS
Internal reference (Vref = V
to divider measurements using the VC16,
(8)
PACK, and LD pins relative to VSS.
16-bit, best fit over -0.1 V to 5.5 V
REF1
16-bit, best fit over -0.2 V to 0.2 V
(4)
16-bit, no missing codes, using differential
cell voltage measurement at VC16-VC15
16-bit, uncalibrated, using VC16 - VC15
16-bit, uncalibrated, using ADCIN mode on
TS1 pin
16-bit, uncalibrated, using divider mode on
PACK pin
Offset error measured 16-bit, post calibration,
using VC16 - VC15. Drift measured as
(4)
change in offset over operating temperature
range as compared to offset at 30°C.
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode on
VC16-VC15, uncalibrated.
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode
on VC16-VC15, uncalibrated. Drift value
(4)
measured as change in gain over operating
temperature range, compared to gain at
30°C.
Differential cell input mode on VC16-VC15
(3)
Divider measurement on LD pin (only active
while the LD pin is being measured)
Divider measurement on VC16 and PACK
pins (only active while the pin is being
measured)
Single conversion, in NORMAL
(2) (4)
mode, Settings:Configuration:Power
Config[FASTADC] = 0
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[FASTADC] = 1
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[FASTADC] = 0
Single conversion, in NORMAL
mode, Settings:Configuration:Power
Config[FASTADC] = 1
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
BAT
Product Folder Links:
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
= -40°C to 85°C and V
A
MIN
), applicable
REF1
–0.2
–6.6
–4
–2.75
5385
-0.25
(9)
2.1
13.5
BQ76952
BQ76952
= 4.7 V
BAT
TYP
MAX
UNIT
80
V
(5)
6.6
LSB
(5)
4
LSB
(5)
±0.12
LSB
(5)
3.5
LSB
(6)
0.53
LSB
(8)
0.17
LSB
(5)
0.004
0.07 LSB/°C
(5)
5406
5427 LSB/V
LSB/V/
0.025
0.25
(5)
°C
MΩ
2
MΩ
600
kΩ
15
bits
14
bits
2.93
ms
1.46
ms
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