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BQ76952
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
was not updated by the internal logic before the transaction occurred. This can occur when the device did not
have sufficient time to update the buffer between consecutive transactions.
When the internal logic takes the write-data from the interface logic and processes it, it also causes the R/W bit,
address, and data to be copied into the outgoing buffer. On the next transaction, this data is clocked back to the
controller.
When the controller is initiating a read, the internal logic puts the R/W bit and address into the outgoing buffer,
along with the data requested. The interface computes the CRC on the two bytes in the outgoing buffer and
clocks that back to the controller if CRC is enabled (with the exceptions associated with 0xFFFF, as noted
above). Below are diagrams of three transaction sequences with and without CRC, assuming CPOL = 0.
SPI_CS
SPI_SCLK
SPI_MOSI
SPI_MISO
58
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R/W bit & 7-bit
address # 1
Previous R/W bit
& 7-bit address
Figure 14-5. SPI Transaction #1 Using CRC
Product Folder Links:
8-bit write
data # 1
Previous 8-bit
write or read data
BQ76952
www.ti.com
8-bit CRC
(for previous
two bytes)
8-bit CRC
(for previous
two bytes)
Copyright © 2021 Texas Instruments Incorporated
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