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is considered invalid. On the next transaction, the CRC (if clocked out) will be 0xAA, so the 0xFFFFAA will
indicate to the controller that a CRC error was detected.
The internal oscillator in the BQ76952 device may not be running when the host initiates a transaction (for
example, this can occur if the device is in SLEEP mode). If this occurs, the interface will drive out 0xFFFF on
SPI_MISO for the first 16-bits clocked out. It will also drive out 0xFF for the third (CRC) byte as well, if CRC is
enabled. So the 0xFFFF or 0xFFFFFF will indicate to the controller that the internal oscillator is not ready yet.
The device will automatically wake the internal oscillator at a falling edge of SPI_CS, but it may take up to 50 µs
to stabilize and be available for use to the SPI interface logic. The address 0x7F used in the device is defined
in such a manner that there should be no valid transaction to write 0xFF into this address. Thus the two-byte
pattern 0xFFFF should never occur as a valid sequence in the first two bytes of a transaction (that is, it is only
used as a flag that something is wrong, similar to an I
Due to the delay in the HFO powering up if initially off, the device includes a programmable hysteresis to cause
the HFO to stay powered for a programmable number of seconds after it is wakened by a falling edge on
SPI_CS. This hysteresis is controlled by the Settings:Configuration:Comm Idle Time configuration setting,
which can be set from 0 to 255 seconds (while in SPI mode, the device will use a minimum hysteresis of 1
second even if the value is set to 0). The host can set this to a longer time (up to 255 seconds) and maintain
regular communications within this time window, causing the HFO to stay powered, so the device can respond
quickly to SPI transactions. However, keeping the HFO running continuously will cause the device to consume
additional supply current beyond what it would consume if the HFO were only powered when needed (the HFO
draws ≈30 µA when powered). To avoid this extra supply current, the host can send an initial, unnecessary SPI
transaction to cause the HFO to waken, and retry this until a valid response is returned on SPI_MISO. At this
point, the host can begin sending the intended SPI transactions.
If an excessive number of SPI transactions occur over a long period of time, the device may experience a
watchdog fault. It is recommended to limit the frequency of SPI transactions by providing 50 μs or more from the
end of one transaction to the start of a new transaction.
The device includes ability to detect a frozen or disconnected SPI bus condition, and it will then reset the bus
logic. This condition is recognized when the SPI_CS is low and the SPI_SCLK is static and not changing for a
two second timeout.
Depending on the version of the device being used, the SPI_MISO pin may be configured by default
to use the REG18 LDO for its output drive, which will result in a 1.8-V signal level. This may cause
communications errors if the host processor operates with a higher voltage, such as 3.3 V or 5 V. The
SPI_MISO pin can be programmed to instead use the REG1 LDO for its output drive by setting the
Settings:Configuration:SPI Configuration[MISO_REG1] data memory configuration bit. This bit should
only be set if the REG1 LDO is powered. After this bit has been modified, it is necessary to send the
SWAP_TO_SPI() or SWAP_COMM_MODE() subcommands for the device to use the new value.
The device includes optional pin filtering on the SPI input pins, which implements a filter with approximately
200 ns delay on each input pin. This filtering is enabled by default but can be disabled by clearing the
Settings:Configuration:SPI Configuration[FILT] data memory configuration bit.
14.3.1 SPI Protocol
The first byte of a SPI transaction consists of an R/W bit (R = 0, W = 1), followed by a 7-bit address, MSB first.
If the controller (host) is writing, then the second byte is the data written. If the controller is reading, then the
second byte sent on SPI_MOSI is ignored (except for CRC calculation).
If CRC is enabled, then the controller must send as the third byte the 8-bit CRC code, which is calculated over
the first two bytes. If the CRC is correct, then the values clocked in will be put into the incoming buffer. If the
CRC is not correct, then the outgoing buffer is set to 0xFFFF, and the outgoing CRC is set to 0xAA (these are
clocked out on the next transaction).
During this transaction, the logic clocks out the contents of the outgoing buffer. If the outgoing buffer was not
updated since the last transaction, then the logic will clock out 0xFFFF; and if the CRC is clocked, it will clock out
0x00 for the CRC (if enabled). Thus, the 0xFFFF00 command indicates to the controller that the outgoing buffer
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2
C NACK).
Product Folder Links:
BQ76952
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
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